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antlr-mode.elc	77.56 KB	-rw-r--r--
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Code Editor : verilog-mode.elc

;ELC���
;;; Compiled
;;; in Emacs version 27.1
;;; with all optimizations.

;;; This file uses dynamic docstrings, first added in Emacs 19.29.

;;; This file does not contain utf-8 non-ASCII characters,
;;; and so can be loaded in Emacs versions earlier than 23.

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

#@31 Version of this Verilog mode.
(defconst verilog-mode-version "2019-12-17-ffa2ba5-vpo-GNU" (#$ . 408))
#@74 If non-nil, this version of Verilog mode was released with Emacs itself.
(defconst verilog-mode-release-emacs t (#$ . 516))
#@44 Inform caller of the version of this file.
(defalias 'verilog-version #[nil "\301\302\"\207" [verilog-mode-version message "Using verilog-mode version %s"] 3 (#$ . 646) nil])
(byte-code "\301\302\303\"\210\304\305!\203�\301\306\305\"\210\202�\301\306\307\"\210\304\310!\203&�\301\311\310\"\210\202+�\301\311\312\"\210\304\313!\2039�\301\314\313\"\210\202>�\301\314\315\"\210\3161I�\317\320!0\202M�\210\202N�\210\3211Y�\317\322!0\202]�\210\202^�\210\3231s�\304\324!?\205o�\301\324\325\326B\"0\202w�\210\202x�\210\304\327!\204\221�\301\327\325\330B\"\331\327\332\333#\210\334\327\335\336#\266\3371\304\340!?\205\341\342!\210\343\344N\204\254�\331\343\344\345#\210\346\347!\204\270�\331\347\350\340#\210\351\352 !\210\347\344N\204\313�\331\347\344\353\354!#\210\346\355!\204\334�\331\355\350\340#\210\356\357 !\210\355\344N\204\352�\331\355\344\353\360!#\210\346\300!\204\377�\331\300\350\340#\210\361\362\300\342\"\210!\210\300\344N\204
\331\300\344\353\363!#\210\331\340\364\342#\210\301\340\365\"0\202\210\202 \210\36611\304\367!?\205/\301\367\370\"0\207\210\342\207" [prog-mode-abbrev-table defalias verilog-regexp-opt regexp-opt fboundp looking-back verilog-looking-back #[(regexp limit &optional greedy) "`\212\305\306\307Q	\310#\205�`)\f\203H�\n\203H�\214e}\210\neV\203<�\212\nb\210\311u\210\312\306\313Q!)\203<�\nS\211\202�\212\nb\210\312\306\313Q!\210*\n*??\207" [regexp limit pos start greedy re-search-backward "\$?:" "\$\\=" t -1 looking-at "\\)\\'"] 6 "Return non-nil if text before point matches regular expression REGEXP.\nLike `looking-at' except matches before point, and is slower.\nLIMIT if non-nil speeds up the search by specifying a minimum\nstarting position, to avoid checking matches that would start\nbefore LIMIT.\n\nIf GREEDY is non-nil, extend the match backwards as far as\npossible, stopping when a single additional previous character\ncannot be part of a match for REGEXP.  When the match is\nextended, its starting position is allowed to occur before\nLIMIT.\n\nAs a general recommendation, try to avoid using `looking-back'\nwherever possible, since it is slow."] restore-buffer-modified-p verilog-restore-buffer-modified-p set-buffer-modified-p quit-window verilog-quit-window #[(kill-ignored window) "\301!\207" [window delete-window] 2 "Quit WINDOW and bury its buffer. KILL-IGNORED is ignored."] (error) require diff (error) compile (error) buffer-chars-modified-tick macro #[nil "\300 \207" [buffer-modified-tick] 1] ignore-errors #[(&rest body) "\301\302\303B\304BBB\207" [body condition-case nil progn ((error nil))] 4] put edebug-form-spec t function-put lisp-indent-function 0 (error) prog-mode (lambda (#1=#:def-tmp-var) (defvar prog-mode-hook #1#)) nil prog-mode-hook variable-documentation "Hook run after entering Prog mode.\nNo problems result if this variable is not bound.\n`add-hook' automatically binds it.  (This is true for all hook variables.)" boundp prog-mode-map definition-name (lambda (#1#) (defvar prog-mode-map #1#)) make-sparse-keymap purecopy "Keymap for `prog-mode'." prog-mode-syntax-table (lambda (#1#) (defvar prog-mode-syntax-table #1#)) make-syntax-table "Syntax table for `prog-mode'." (lambda (#1#) (defvar prog-mode-abbrev-table #1#)) define-abbrev-table "Abbrev table for `prog-mode'." derived-mode-parent #[nil "\306\300!\210\307\310 \210\311\312\313!\210\314\f!\210
)\315\316!\207" [delay-mode-hooks major-mode mode-name prog-mode-map prog-mode-syntax-table prog-mode-abbrev-table make-local-variable t kill-all-local-variables prog-mode "Prog" use-local-map set-syntax-table run-mode-hooks prog-mode-hook local-abbrev-table] 2 "Major-mode.\nUses keymap `prog-mode-map', abbrev table `prog-mode-abbrev-table' and syntax-table `prog-mode-syntax-table'.\n\nThis mode runs the hook `prog-mode-hook', as the final or penultimate step\nduring initialization.\n\n\\{prog-mode-map}" nil] (error) forward-word-strictly forward-word] 5)
#@57 Call `regexp-opt' with word delimiters for the words A.
(defalias 'verilog-regexp-words #[(a) "\301\302\303\"\304Q\207" [a "\\<" verilog-regexp-opt t "\\>"] 4 (#$ . 4588)])
#@57 Filter `easy-menu-define' MENU to support new features.
(defalias 'verilog-easy-menu-filter #[(menu) "\207" [menu] 1 (#$ . 4768)])
#@100 Filter `define-abbrev-table' TABLENAME DEFINITIONS
Provides DOCSTRING PROPS in newer Emacs (23.1).
(defalias 'verilog-define-abbrev-table #[(tablename definitions &optional docstring &rest props) "\3041
�\305\306	\n%0\207\210\306	\"\207" [tablename definitions docstring props (error) apply define-abbrev-table] 6 (#$ . 4907)])
#@97 Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
Provides SYSTEM-FLAG in newer Emacs.
(defalias 'verilog-define-abbrev #[(table name expansion &optional hook) "\3041�\305	\n\306\307&0\207\210\305	\n$\207" [table name expansion hook (error) define-abbrev 0 t] 7 (#$ . 5244)])
#@62 Customize variables and other settings used by Verilog-Mode.
(defalias 'verilog-customize #[nil "\300\301!\207" [customize-group verilog-mode] 2 (#$ . 5541) nil])
#@39 Customize fonts used by Verilog-Mode.
(defalias 'verilog-font-customize #[nil "\300\301!\205\n�\301\302\303\"\207" [fboundp customize-apropos "font-lock-*" faces] 3 (#$ . 5710) nil])
#@169 Return t if VALUE is boolean.
This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs.
This function may be removed when Emacs 21 is no longer supported.
(defalias 'verilog-booleanp #[(value) "\301=\206	�\302=\207" [value t nil] 2 (#$ . 5900)])
#@34 Insert the `last-command-event'.
(defalias 'verilog-insert-last-command-event #[nil "c\207" [last-command-event] 1 (#$ . 6167)])
#@114 True if `after-change-functions' is disabled.
Use of `syntax-ppss' may break, as ppss's cache may get corrupted.
(defvar verilog-no-change-functions nil (#$ . 6304))
#@47 True when within a `verilog-run-hooks' block.
(defvar verilog-in-hooks nil (#$ . 6476))
#@107 Run each hook in HOOKS using `run-hooks'.
Set `verilog-in-hooks' during this time, to assist AUTO caches.
(defalias 'verilog-run-hooks '(macro . #[(&rest hooks) "\301\302\303BE\207" [hooks let ((verilog-in-hooks t)) run-hooks] 4 (#$ . 6571)]))
(defalias 'verilog-syntax-ppss #[(&optional pos) "\203�	\203�\303 \210\202�\304 \210\305\306\307 \"\210\310\311!\203!�\311\n!\207\312e\n\206(�`\"\207" [verilog-no-change-functions verilog-in-hooks pos verilog-scan-cache-flush backtrace error "%s: Internal problem; use of syntax-ppss when cache may be corrupt" verilog-point-text fboundp syntax-ppss parse-partial-sexp] 3])
(byte-code "\300\301\302\303\304\305\306\307&\210\300\310\302\311\306\301%\210\300\312\302\313\306\301%\210\300\314\302\315\306\301%\207" [custom-declare-group verilog-mode nil "Major mode for Verilog source code." :version "22.2" :group languages verilog-mode-indent "Customize indentation and highlighting of Verilog source text." verilog-mode-actions "Customize actions on Verilog source text." verilog-mode-auto "Customize AUTO actions when expanding Verilog source text."] 8)
#@67 Non-nil means enable debug messages for `verilog-mode' internals.
(defvar verilog-debug nil (#$ . 7682))
#@65 Non-nil means `verilog-warn-error' warnings are fatal `error's.
(defvar verilog-warn-fatal nil (#$ . 7793))
(byte-code "\300\301\302\303\304\305\306\307&\210\300\310\311\312\304\305\306\307&\210\300\313\314\315\304\305\306\307&\210\300\316\317\320\304\305\306\307&\210\300\321\322\323\304\305\306\307&\207" [custom-declare-variable verilog-linter "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'" "Unix program and arguments to call to run a lint checker on Verilog source.\nDepending on the `verilog-set-compile-command', this may be invoked when\nyou type \\[compile].  When the compile completes, \\[next-error] will take\nyou to the next lint error." :type string :group verilog-mode-actions verilog-coverage "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'" "Program and arguments to use to annotate for coverage Verilog source.\nDepending on the `verilog-set-compile-command', this may be invoked when\nyou type \\[compile].  When the compile completes, \\[next-error] will take\nyou to the next lint error." verilog-simulator "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'" "Program and arguments to use to interpret Verilog source.\nDepending on the `verilog-set-compile-command', this may be invoked when\nyou type \\[compile].  When the compile completes, \\[next-error] will take\nyou to the next lint error." verilog-compiler "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'" "Program and arguments to use to compile Verilog source.\nDepending on the `verilog-set-compile-command', this may be invoked when\nyou type \\[compile].  When the compile completes, \\[next-error] will take\nyou to the next lint error." verilog-preprocessor "verilator -E __FLAGS__ __FILE__" "Program and arguments to use to preprocess Verilog source.\nThis is invoked with `verilog-preprocess', and depending on the\n`verilog-set-compile-command', may also be invoked when you type\n\\[compile].  When the compile completes, \\[next-error] will\ntake you to the next lint error."] 8)
#@35 History for `verilog-preprocess'.
(defvar verilog-preprocess-history nil (#$ . 9902))
#@281 Which tool to use for building compiler-command.
Either nil, `verilog-linter', `verilog-compiler',
`verilog-coverage', `verilog-preprocessor', or `verilog-simulator'.
Alternatively use the "Choose Compilation Action" menu.  See
`verilog-set-compile-command' for more information.
(defvar verilog-tool 'verilog-linter (#$ . 9995))
(byte-code "\300\301\302\303\304\305\306\307&\210\310\301\311\312#\210\300\313\314\315\304\316\306\307&\210\310\313\311\317#\210\300\320\321\322\306\307\304\323&\210\310\320\311\324#\210\300\325\321\326\306\307\304\323&\210\310\325\311\324#\210\300\327\321\330\306\307\304\323&\210\310\327\311\324#\210\300\331\302\332\306\307\304\305&\210\310\331\311\312#\210\300\333\334\335\306\307\304\305&\210\310\333\311\312#\210\300\336\321\337\306\307\304\323&\210\310\336\311\324#\210\300\340\341\342\306\307\304\323&\210\310\340\311\324#\210\300\343\344\345\306\307\304\323&\210\310\343\311\324#\210\300\346\344\347\306\307\304\323&\210\310\346\311\324#\210\300\350\334\351\306\307\304\305&\210\310\350\311\312#\210\300\352\334\353\306\307\304\305&\210\310\352\311\312#\210\300\354\334\355\306\307\304\305&\210\310\354\311\312#\210\300\356\302\357\306\360\304\305&\210\310\356\311\312#\210\300\361\334\362\306\307\304\305&\210\310\361\311\312#\210\300\363\302\364\306\307\304\305&\210\310\363\311\312#\210\300\365\366\367\306\307\304\323&\210\310\365\311\324#\210\300\370\302\371\306\307\304\305&\210\310\370\311\312#\210\372\370\302\373#\210\300\374\302\375\306\307\304\305&\210\310\374\311\312#\210\300\376\302\377\306\307\304\305&\210\310\376\311\312#\210\300\201@�\334\201A�\306\307\304\305&\210\310\201@�\311\312#\210\300\201B�\302\201C�\201D�\201E�\306\360\304\305&	\210\310\201B�\311\201F�#\210\300\201G�\334\201H�\201D�\201I�\306\360\304\305&	\210\310\201G�\311\312#\210\300\201J�\302\201K�\201D�\201E�\306\360\304\201L�&	\210\310\201J�\311\201F�#\210\300\201M�\334\201N�\306\360\304\305&\210\310\201M�\311\312#\210\300\201O�\302\201P�\201D�\201E�\306\360\304\305&	\210\310\201O�\311\312#\210\300\201Q�\302\201R�\306\360\304\305&\210\310\201Q�\311\312#\210\300\201S�\302\201T�\306\360\304\305&\210\310\201S�\311\312#\210\300\201U�\302\201V�\306\360\304\201W�&\210\300\201X�\334\201Y�\306\360\304\305&\210\310\201X�\311\312#\210\300\201Z�\302\201[�\306\360\304\305&\210\310\201Z�\311\312#\207" [custom-declare-variable verilog-highlight-translate-off nil "Non-nil means background-highlight code excluded from translation.\nThat is, all code between \"// synopsys translate_off\" and\n\"// synopsys translate_on\" is highlighted using a different background color\n(face `verilog-font-lock-translate-off-face').\n\nNote: This will slow down on-the-fly fontification (and thus editing).\n\nNote: Activate the new setting in a Verilog buffer by re-fontifying it (menu\nentry \"Fontify Buffer\").  XEmacs: turn off and on font locking." :type boolean :group verilog-mode-indent put safe-local-variable verilog-booleanp verilog-auto-lineup 'declarations "Type of statements to lineup across multiple lines.\nIf `all' is selected, then all line ups described below are done.\n\nIf `declarations', then just declarations are lined up with any\npreceding declarations, taking into account widths and the like,\nso or example the code:\n	reg [31:0] a;\n	reg b;\nwould become\n	reg [31:0] a;\n	reg        b;\n\nIf `assignment', then assignments are lined up with any preceding\nassignments, so for example the code\n	a_long_variable <= b + c;\n	d = e + f;\nwould become\n	a_long_variable <= b + c;\n	d                = e + f;\n\nIn order to speed up editing, large blocks of statements are lined up\nonly when a \\[verilog-pretty-expr] is typed; and large blocks of declarations\nare lineup only when \\[verilog-pretty-declarations] is typed." (radio (const :tag "Line up Assignments and Declarations" all) (const :tag "Line up Assignment statements" assignments) (const :tag "Line up Declarations" declarations) (function :tag "Other")) (lambda (x) (memq x '(nil all assignments declarations))) verilog-indent-level 3 "Indentation of Verilog statements with respect to containing block." integer integerp verilog-indent-level-module "Indentation of Module level Verilog statements (eg always, initial).\nSet to 0 to get initial and always statements lined up on the left side of\nyour screen." verilog-indent-level-declaration "Indentation of declarations with respect to containing block.\nSet to 0 to get them list right under containing block." verilog-indent-declaration-macros "How to treat macro expansions in a declaration.\nIf nil, indent as:\n	input [31:0] a;\n	input        \\=`CP;\n	output       c;\nIf non-nil, treat as:\n	input [31:0] a;\n	input \\=`CP    ;\n	output       c;" verilog-indent-lists t "How to treat indenting items in a list.\nIf t (the default), indent as:\n	always @( posedge a or\n	          reset ) begin\n\nIf nil, treat as:\n	always @( posedge a or\n	   reset ) begin" verilog-indent-level-behavioral "Absolute indentation of first begin in a task or function block.\nSet to 0 to get such code to start at the left side of the screen." verilog-indent-level-directive 1 "Indentation to add to each level of \\=`ifdef declarations.\nSet to 0 to have all directives start at the left side of the screen." verilog-cexp-indent 2 "Indentation of Verilog statements split across lines." verilog-case-indent "Indentation for case statements." verilog-auto-newline "Non-nil means automatically newline after semicolons." verilog-auto-indent-on-newline "Non-nil means automatically indent line after newline." verilog-tab-always-indent "Non-nil means TAB should always re-indent the current line.\nA nil value means TAB will only reindent when at the beginning of the line." verilog-tab-to-comment "Non-nil means TAB moves to the right hand column in preparation for a comment." verilog-mode-actions verilog-indent-begin-after-if "Non-nil means indent begin statements following if, else, while, etc.\nOtherwise, line them up." verilog-align-ifelse "Non-nil means align `else' under matching `if'.\nOtherwise else is lined up with first character on line holding matching if." verilog-minimum-comment-distance 10 "Minimum distance (in lines) between begin and end required before a comment.\nSetting this variable to zero results in every end acquiring a comment; the\ndefault avoids too many redundant comments in tight quarters." verilog-highlight-p1800-keywords "Obsolete.\nWas non-nil means highlight SystemVerilog IEEE-1800 differently.\nAll code is now highlighted as if SystemVerilog IEEE-1800." make-obsolete-variable "27.1" verilog-highlight-grouping-keywords "Non-nil means highlight grouping keywords more dramatically.\nIf false, these words are in the `font-lock-type-face'; if True\nthen they are in `verilog-font-lock-grouping-keywords-face'.\nSome find that special highlighting on these grouping constructs\nallow the structure of the code to be understood at a glance." verilog-highlight-modules "Non-nil means highlight module statements for `verilog-load-file-at-point'.\nWhen true, mousing over module names will allow jumping to the\nmodule definition.  If false, this is not supported.  Setting\nthis is experimental, and may lead to bad performance." verilog-highlight-includes "Non-nil means highlight module statements for `verilog-load-file-at-point'.\nWhen true, mousing over include file names will allow jumping to the\nfile referenced.  If false, this is not supported." verilog-auto-declare-nettype "Non-nil specifies the data type to use with `verilog-auto-input' etc.\nSet this to \"wire\" if the Verilog code uses \"\\=`default_nettype\nnone\".  Note using \\=`default_nettype none isn't recommended practice; this\nmode is experimental." :version "24.1" stringp verilog-auto-wire-comment "Non-nil indicates to insert to/from comments with `verilog-auto-wire' etc." "25.1" verilog-auto-wire-type "Non-nil specifies the data type to use with `verilog-auto-wire' etc.\nSet this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'.\nSet this to \"wire\" to force use of wire when logic is otherwise appropriate;\nthis is generally only appropriate when making a non-SystemVerilog wrapper\ncontaining SystemVerilog cells." (choice (const nil) string) verilog-auto-endcomments "Non-nil means insert a comment /* ... */ after `end's.\nThe name of the function or case will be set between the braces." verilog-auto-delete-trailing-whitespace "Non-nil means to `delete-trailing-whitespace' in `verilog-auto'." verilog-auto-ignore-concat "Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.\nThis will exclude signals referenced as pin connections in {...}\nor (...) from AUTOWIRE, AUTOOUTPUT and friends." verilog-auto-read-includes "Non-nil means to automatically read includes before AUTOs.\nThis will do a `verilog-read-defines' and `verilog-read-includes' before\neach AUTO expansion.  This makes it easier to embed defines and includes,\nbut can result in very slow reading times if there are many or large\ninclude files." verilog-auto-save-policy "Non-nil indicates action to take when saving a Verilog buffer with AUTOs.\nA value of `force' will always do a \\[verilog-auto] automatically if\nneeded on every save.  A value of `detect' will do \\[verilog-auto]\nautomatically when it thinks necessary.  A value of `ask' will query the\nuser when it thinks updating is needed.\n\nYou should not rely on the `ask' or `detect' policies, they are safeguards\nonly.  They do not detect when AUTOINSTs need to be updated because a\nsub-module's port list has changed." (choice (const nil) (const ask) (const detect) (const force)) verilog-auto-star-expand "Non-nil means to expand SystemVerilog .* instance ports.\nThey will be expanded in the same way as if there was an AUTOINST in the\ninstantiation.  See also `verilog-auto-star' and `verilog-auto-star-save'." verilog-auto-star-save "Non-nil means save to disk SystemVerilog .* instance expansions.\nA nil value indicates direct connections will be removed before saving.\nOnly meaningful to those created due to `verilog-auto-star-expand' being set.\n\nInstead of setting this, you may want to use /*AUTOINST*/, which will\nalways be saved."] 10)
#@55 Modification tick at which autos were last performed.
(defvar verilog-auto-update-tick nil (#$ . 20239))
#@56 Text from file-local-variables during last evaluation.
(defvar verilog-auto-last-file-locals nil (#$ . 20350))
#@199 Function to run when `verilog-diff-auto' detects differences.
Function takes three arguments, the original buffer, the
difference buffer, and the point in original buffer with the
first difference.
(defvar verilog-diff-function 'verilog-diff-report (#$ . 20468))
#@88 Non-nil specifies regexp which `verilog-diff-auto' will ignore.
This is typically nil.
(defvar verilog-diff-ignore-regexp nil (#$ . 20737))
(require 'compile)
(defvar verilog-error-regexp-added nil)
#@113 List of regexps for Verilog compilers.
See `compilation-error-regexp-alist' for the formatting.  For Emacs 22+.
(defvar verilog-error-regexp-emacs-alist '((verilog-xl-1 "\$Error\\|Warning\$!.*\n?.*\"\$[^\"]+\$\", \$[0-9]+\$" 2 3) (verilog-xl-2 "([WE][0-9A-Z]+)[ 	]+\$[^ 	\n,]+\$[, 	]+\$line[ 	]+\$?\$[0-9]+\$:.*$" 1 3) (verilog-IES ".*\\*[WE],[0-9A-Z]+\$\\[[0-9A-Z_,]+\\]\$? (\$[^ 	,]+\$,\$[0-9]+\$" 2 3) (verilog-surefire-1 "[^\n]*\\[\$[^:]+\$:\$[0-9]+\$\\]" 1 2) (verilog-surefire-2 "\$WARNING\\|ERROR\\|INFO\$[^:]*: \$[^,]+\$,\\s-+\$line \$?\$[0-9]+\$:" 2 4) (verilog-verbose "\$[a-zA-Z]?:?[^:( 	\n]+\$[:(][ 	]*\$[0-9]+\$\$[) 	]\\|:\\([^0-9\n]\\|\\([0-9]+:\$\\)\\)" 1 2 5) (verilog-xsim "\$Error\\|Warning\$.*in file (\$[^ 	]+\$ at line *\$[0-9]+\$)" 2 3) (verilog-vcs-1 "\$Error\\|Warning\$:[^(]*(\$[^ 	]+\$ line *\$[0-9]+\$)" 2 3) (verilog-vcs-2 "Warning:.*(port.*(\$[^ 	]+\$ line \$[0-9]+\$)" 1 2) (verilog-vcs-3 "\$Error\\|Warning\$:[\n.]*\$[^ 	]+\$ *\$[0-9]+\$:" 2 3) (verilog-vcs-4 "syntax error:.*\n\$[^ 	]+\$ *\$[0-9]+\$:" 1 2) (verilog-verilator "%?\$Error\\|Warning\$\$-[^:]+\\|\$:[\n ]*\$[^ 	:]+\$:\$[0-9]+\$:" 3 4) (verilog-leda "^In file \$[^ 	]+\$[ 	]+line[ 	]+\$[0-9]+\$:\n[^\n]*\n[^\n]*\n\$Warning\\|Error\\|Failure\$[^\n]*" 1 2)) (#$ . 20943))
#@116 List of regexps for Verilog compilers.
See `compilation-error-regexp-alist-alist' for the formatting.  For XEmacs.
(defvar verilog-error-regexp-xemacs-alist (byte-code "\301\302\303\"B\207" [verilog-error-regexp-emacs-alist verilog mapcar cdr] 4) (#$ . 22290))
#@134 Keywords to also highlight in Verilog *compilation* buffers.
Only used in XEmacs; GNU Emacs uses `verilog-error-regexp-emacs-alist'.
(defvar verilog-error-font-lock-keywords '(("\$Error\\|Warning\$!.*\n?.*\"\$[^\"]+\$\", \$[0-9]+\$" 2 bold t) ("\$Error\\|Warning\$!.*\n?.*\"\$[^\"]+\$\", \$[0-9]+\$" 2 bold t) ("([WE][0-9A-Z]+)[ 	]+\$[^ 	\n,]+\$[, 	]+\$line[ 	]+\$?\$[0-9]+\$:.*$" 1 bold t) ("([WE][0-9A-Z]+)[ 	]+\$[^ 	\n,]+\$[, 	]+\$line[ 	]+\$?\$[0-9]+\$:.*$" 3 bold t) (".*\\*[WE],[0-9A-Z]+\$\\[[0-9A-Z_,]+\\]\$? (\$[^ 	,]+\$,\$[0-9]+\$|" 2 bold t) (".*\\*[WE],[0-9A-Z]+\$\\[[0-9A-Z_,]+\\]\$? (\$[^ 	,]+\$,\$[0-9]+\$|" 3 bold t) ("[^\n]*\\[\$[^:]+\$:\$[0-9]+\$\\]" 1 bold t) ("[^\n]*\\[\$[^:]+\$:\$[0-9]+\$\\]" 2 bold t) ("\$WARNING\\|ERROR\\|INFO\$: \$[^,]+\$, line \$[0-9]+\$:" 2 bold t) ("\$WARNING\\|ERROR\\|INFO\$: \$[^,]+\$, line \$[0-9]+\$:" 3 bold t) ("\$[a-zA-Z]?:?[^:( 	\n]+\$[:(][ 	]*\$[0-9]+\$\$[) 	]\\|:\\([^0-9\n]\\|\\([0-9]+:\$\\)\\)" 1 bold t) ("\$[a-zA-Z]?:?[^:( 	\n]+\$[:(][ 	]*\$[0-9]+\$\$[) 	]\\|:\\([^0-9\n]\\|\\([0-9]+:\$\\)\\)" 1 bold t) ("\$Error\\|Warning\$:[^(]*(\$[^ 	]+\$ line *\$[0-9]+\$)" 2 bold t) ("\$Error\\|Warning\$:[^(]*(\$[^ 	]+\$ line *\$[0-9]+\$)" 3 bold t) ("Warning:.*(port.*(\$[^ 	]+\$ line \$[0-9]+\$)" 1 bold t) ("Warning:.*(port.*(\$[^ 	]+\$ line \$[0-9]+\$)" 1 bold t) ("\$Error\\|Warning\$:[\n.]*\$[^ 	]+\$ *\$[0-9]+\$:" 2 bold t) ("\$Error\\|Warning\$:[\n.]*\$[^ 	]+\$ *\$[0-9]+\$:" 3 bold t) ("syntax error:.*\n\$[^ 	]+\$ *\$[0-9]+\$:" 1 bold t) ("syntax error:.*\n\$[^ 	]+\$ *\$[0-9]+\$:" 2 bold t) (".*%?\$Error\\|Warning\$\$-[^:]+\\|\$:[\n ]*\$[^ 	:]+\$:\$[0-9]+\$:" 3 bold t) (".*%?\$Error\\|Warning\$\$-[^:]+\\|\$:[\n ]*\$[^ 	:]+\$:\$[0-9]+\$:" 4 bold t) ("^In file \$[^ 	]+\$[ 	]+line[ 	]+\$[0-9]+\$:\n[^\n]*\n[^\n]*\n\$Warning\\|Error\\|Failure\$[^\n]*" 1 bold t) ("^In file \$[^ 	]+\$[ 	]+line[ 	]+\$[0-9]+\$:\n[^\n]*\n[^\n]*\n\$Warning\\|Error\\|Failure\$[^\n]*" 2 bold t)) (#$ . 22559))
(byte-code "\300\301\302\303\304\305\306\307&\210\310\301\311\312#\210\300\313\314\315\304\305\306\316&\210\310\313\311\312#\210\300\317\320\321\304\305\306\322&\210\310\317\311\312#\210\300\323\324\325\306\326\304\305&\210\310\323\311\312#\210\300\327\330\331\304\305\306\332&\210\310\327\311\333#\210\300\334\330\335\304\305\306\336&\210\310\334\311\337#\210\300\340\330\341\304\305\306\336&\210\310\340\311\337#\210\300\342\343\344\345\346\304\305\306\336&	\210\310\342\311\337#\210\300\347\343\350\345\351\306\336\304\305&	\210\310\347\311\337#\210\300\352\343\353\306\336\304\305&\210\310\352\311\354#\210\300\355\356\357\304\305\306\360&\210\310\355\311\333#\210\300\361\362\363\345\364\306\365\304\305&	\210\310\361\311\366#\210\300\367\330\370\304\305\306\336&\210\310\367\311\337#\210\300\371\330\372\304\305\306\336&\210\310\371\311\337#\210\300\373\330\374\304\305\306\336&\210\310\373\311\337#\210\300\375\343\376\345\364\304\305\306\336&	\210\310\375\311\337#\210\300\377\330\201@�\345\351\304\305\306\336&	\210\310\377\311\337#\210\300\201A�\343\201B�\304\305\306\201C�&\210\310\201A�\311\201D�#\210\300\201E�\330\201F�\304\305\306\201G�&\210\310\201E�\311\201H�#\210\300\201I�\201J�\201K�\304\201L�\306\201M�&\210\310\201I�\311\201N�#\210\300\201O�\330\201P�\345\201Q�\304\305\306\336&	\210\310\201O�\311\337#\210\300\201R�\330\201S�\304\305\306\201T�&\210\310\201R�\311\333#\210\300\201U�\330\201V�\345\346\304\305\306\201W�&	\210\310\201U�\311\333#\210\300\201X�\330\201Y�\304\305\306\201Z�&\210\310\201X�\311\333#\210\300\201[�\330\201\\�\304\305\306\201]�&\210\310\201[�\311\333#\210\300\201^�\330\201_�\345\201Q�\304\305\306\336&	\210\310\201^�\311\337#\210\300\201`�\201a�\201b�\345\351\304\305\306\360&	\210\310\201`�\311\333#\210\300\201c�\330\201d�\304\305\306\201e�&\210\310\201c�\311\333#\210\300\201f�\330\201g�\304\305\306\201h�&\210\310\201f�\311\333#\210\300\201i�\343\201j�\345\201k�\304\201l�\306\336&	\210\310\201i�\311\337#\210\300\201m�\330\201n�\304\305\306\201o�&\210\310\201m�\311\333#\210\300\201p�\201q�\201r�\306\201s�\304\201l�&\210\300\201t�\330\201u�\304\305\306\201s�&\210\300\201v�\330\201w�\304\305\306\201s�&\210\300\201x�\330\201y�\304\305\306\201s�&\210\300\201z�\330\201{�\304\305\306\201s�&\210\300\201|�\330\201}�\304\305\306\201s�&\210\300\201~�\330\201�\304\305\306\201s�&\210\300\201\200�\330\201\201�\345\201Q�\304\305\306\201s�&	\210\300\201\202�\330\201\203�\345\201Q�\304\305\306\201s�&	\207" [custom-declare-variable verilog-library-flags '(#1="") "List of standard Verilog arguments to use for /*AUTOINST*/.\nThese arguments are used to find files for `verilog-auto', and match\nthe flags accepted by a standard Verilog-XL simulator.\n\n    -f filename     Reads absolute `verilog-library-flags' from the filename.\n    -F filename     Reads relative `verilog-library-flags' from the filename.\n    +incdir+dir     Adds the directory to `verilog-library-directories'.\n    -Idir           Adds the directory to `verilog-library-directories'.\n    -y dir          Adds the directory to `verilog-library-directories'.\n    +libext+.v      Adds the extensions to `verilog-library-extensions'.\n    -v filename     Adds the filename to `verilog-library-files'.\n\n    filename        Adds the filename to `verilog-library-files'.\n                    This is not recommended, -v is a better choice.\n\nYou might want these defined in each file; put at the *END* of your file\nsomething like:\n\n    // Local Variables:\n    // verilog-library-flags:(\"-y dir -y otherdir\")\n    // End:\n\nVerilog-mode attempts to detect changes to this local variable, but they\nare only insured to be correct when the file is first visited.  Thus if you\nhave problems, use \\[find-alternate-file] RET to have these take effect.\n\nSee also the variables mentioned above." :group verilog-mode-auto :type (repeat string) put safe-local-variable listp verilog-library-directories '(".") "List of directories when looking for files for /*AUTOINST*/.\nThe directory may be relative to the current file, or absolute.\nEnvironment variables are also expanded in the directory names.\nHaving at least the current directory is a good idea.\n\nYou might want these defined in each file; put at the *END* of your file\nsomething like:\n\n    // Local Variables:\n    // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")\n    // End:\n\nVerilog-mode attempts to detect changes to this local variable, but they\nare only insured to be correct when the file is first visited.  Thus if you\nhave problems, use \\[find-alternate-file] RET to have these take effect.\n\nSee also `verilog-library-flags', `verilog-library-files'\nand `verilog-library-extensions'." (repeat file) verilog-library-files 'nil "List of files to search for modules.\nAUTOINST will use this when it needs to resolve a module name.\nThis is a complete path, usually to a technology file with many standard\ncells defined in it.\n\nYou might want these defined in each file; put at the *END* of your file\nsomething like:\n\n    // Local Variables:\n    // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")\n    // End:\n\nVerilog-mode attempts to detect changes to this local variable, but they\nare only insured to be correct when the file is first visited.  Thus if you\nhave problems, use \\[find-alternate-file] RET to have these take effect.\n\nSee also `verilog-library-flags', `verilog-library-directories'." (repeat directory) verilog-library-extensions '(".v" ".va" ".sv") "List of extensions to use when looking for files for /*AUTOINST*/.\nSee also `verilog-library-flags', `verilog-library-directories'." (repeat string) verilog-active-low-regexp nil "If true, treat signals matching this regexp as active low.\nThis is used for AUTORESET and AUTOTIEOFF.  For proper behavior,\nyou will probably also need `verilog-auto-reset-widths' set." (choice (const nil) regexp) stringp verilog-auto-sense-include-inputs "Non-nil means AUTOSENSE should include all inputs.\nIf nil, only inputs that are NOT output signals in the same block are\nincluded." boolean verilog-booleanp verilog-auto-sense-defines-constant "Non-nil means AUTOSENSE should assume all defines represent constants.\nWhen true, the defines will not be included in sensitivity lists.  To\nmaintain compatibility with other sites, this should be set at the bottom\nof each Verilog file that requires it, rather than being set globally." verilog-auto-simplify-expressions t "Non-nil means AUTOs will simplify expressions when calculating bit ranges.\nWhen nil, do not simply ranges, which may simplify the output,\nbut may cause problems when there are multiple instantiations\noutputting to the same wire.  To maintain compatibility with\nother sites, this should be set at the bottom of each Verilog\nfile that requires it, rather than being set globally." :version "27.1" verilog-auto-reset-blocking-in-non "Non-nil means AUTORESET will reset blocking statements.\nWhen true, AUTORESET will reset in blocking statements those\nsignals which were assigned with blocking assignments (=) even in\na block with non-blocking assignments (<=).\n\nIf nil, all blocking assigned signals are ignored when any\nnon-blocking assignment is in the AUTORESET block.  This allows\nblocking assignments to be used for temporary values and not have\nthose temporaries reset.  See example in `verilog-auto-reset'." "24.1" verilog-auto-reset-widths "True means AUTORESET should determine the width of signals.\nThis is then used to set the width of the zero (32'h0 for example).  This\nis required by some lint tools that aren't smart enough to ignore widths of\nthe constant zero.  This may result in ugly code when parameters determine\nthe MSB or LSB of a signal inside an AUTORESET.\n\nIf nil, AUTORESET uses \"0\" as the constant.\n\nIf `unbased', AUTORESET used the unbased unsized literal \"\\='0\"\nas the constant. This setting is strongly recommended for\nSystemVerilog designs." (lambda (x) (memq x '(nil t unbased))) verilog-assignment-delay #1# "Text used for delays in delayed assignments.  Add a trailing space if set." string verilog-auto-arg-format 'packed "Formatting to use for AUTOARG signal names.\nIf `packed', then as many inputs and outputs that fit within\n`fill-column' will be put onto one line.\n\nIf `single', then a single input or output will be put onto each\nline." "25.1" (radio (const :tag "Line up Assignments and Declarations" packed) (const :tag "Line up Assignment statements" single)) (lambda (x) (memq x '(packed single))) verilog-auto-arg-sort "Non-nil means AUTOARG signal names will be sorted, not in declaration order.\nDeclaration order is advantageous with order based instantiations\nand is the default for backward compatibility.  Sorted order\nreduces changes when declarations are moved around in a file, and\nit's bad practice to rely on order based instantiations anyhow.\n\nSee also `verilog-auto-inst-sort'." verilog-auto-inst-dot-name "Non-nil means when creating ports with AUTOINST, use .name syntax.\nThis will use \".port\" instead of \".port(port)\" when possible.\nThis is only legal in SystemVerilog files, and will confuse older\nsimulators.  Setting `verilog-auto-inst-vector' to nil may also\nbe desirable to increase how often .name will be used." verilog-auto-inst-param-value "Non-nil means AUTOINST will replace parameters with the parameter value.\nIf nil, leave parameters as symbolic names.\n\nParameters must be in Verilog 2001 format #(...), and if a parameter is not\nlisted as such there (as when the default value is acceptable), it will not\nbe replaced, and will remain symbolic.\n\nFor example, imagine a submodule uses parameters to declare the size of its\ninputs.  This is then used by an upper module:\n\n        module InstModule (o,i);\n           parameter WIDTH;\n           input [WIDTH-1:0] i;\n           parameter type OUT_t;\n           output OUT_t o;\n        endmodule\n\n        module ExampParamVal1;\n           /*AUTOOUTPUT*/\n           // Beginning of automatic outputs\n           output OUT_t o;\n           // End of automatics\n\n           InstModule\n             #(.WIDTH(10),\n               ,.OUT_t(upper_t))\n            instName\n             (/*AUTOINST*/\n              .o        (o),\n              .i        (i[WIDTH-1:0]));\n        endmodule\n\n       // Local Variables:\n       // verilog-typedef-regexp: \"_t$\"\n       // End:\n\nNote even though WIDTH=10, the AUTOINST has left the parameter as\na symbolic name.  Likewise the OUT_t is preserved as the name\nfrom the instantiated module.\n\nIf `verilog-auto-inst-param-value' is set, this will\ninstead expand to:\n\n        module ExampParamVal1;\n           /*AUTOOUTPUT*/\n           // Beginning of automatic outputs\n           output upper_t o;\n           // End of automatics\n\n           InstModule\n             #(.WIDTH(10),\n               ,.OUT_t(upper_t))\n            instName\n             (/*AUTOINST*/\n              .o        (o),\n              .i        (i[9:0]));\n\nNote that the instantiation now has \"i[9:0]\" as the WIDTH\nwas expanded.  Likewise the data type of \"o\" in the AUTOOUTPUT\nis now upper_t, from the OUT_t parameter override.\nThis second expansion of parameter types can be overridden with\n`verilog-auto-inst-param-value-type'." verilog-auto-inst-param-value-type "Non-nil means expand parameter type in instantiations.\nIf nil, leave parameter types as symbolic names.\n\nSee `verilog-auto-inst-param-value'." verilog-auto-inst-sort "Non-nil means AUTOINST signals will be sorted, not in declaration order.\nAlso affects AUTOINSTPARAM.  Declaration order is the default for\nbackward compatibility, and as some teams prefer signals that are\ndeclared together to remain together.  Sorted order reduces\nchanges when declarations are moved around in a file.\n\nSee also `verilog-auto-arg-sort'." verilog-auto-inst-vector "True means when creating default ports with AUTOINST, use bus subscripts.\nIf nil, skip the subscript when it matches the entire bus as declared in\nthe module (AUTOWIRE signals always are subscripted, you must manually\ndeclare the wire to have the subscripts removed.)  Setting this to nil may\nspeed up some simulators, but is less general and harder to read, so avoid.\nIf `unsigned', use vectors for unsigned types (like using true,\notherwise no vectors if sizes match (like using nil)." (choice (const nil) (const t) (const unsigned)) (lambda (x) (memq x '(nil t unsigned))) verilog-auto-inst-template-numbers "If true, when creating templated ports with AUTOINST, add a comment.\n\nIf t, the comment will add the line number of the template that\nwas used for that port declaration.  This setting is suggested\nonly for debugging use, as regular use may cause a large numbers\nof merge conflicts.\n\nIf `lhs', the comment will show the left hand side of the\nAUTO_TEMPLATE rule that is matched.  This is less precise than\nnumbering (t) when multiple rules have the same pin name, but\nwon't merge conflict." (choice (const nil) (const t) (const lhs)) (lambda (x) (memq x '(nil t lhs))) verilog-auto-inst-column 40 "Indent-to column number for net name part of AUTOINST created pin." verilog-mode-indent integer integerp verilog-auto-inst-interfaced-ports "Non-nil means include interfaced ports in AUTOINST expansions." "24.3" verilog-auto-input-ignore-regexp "If non-nil, when creating AUTOINPUT, ignore signals matching this regexp.\nSee the \\[verilog-faq] for examples on using this." (choice (const nil) regexp) verilog-auto-reg-input-assigned-ignore-regexp "If non-nil, when creating AUTOINPUTREG, ignore signals matching this regexp." (choice (const nil) regexp) verilog-auto-inout-ignore-regexp "If non-nil, when creating AUTOINOUT, ignore signals matching this regexp.\nSee the \\[verilog-faq] for examples on using this." (choice (const nil) regexp) verilog-auto-output-ignore-regexp "If non-nil, when creating AUTOOUTPUT, ignore signals matching this regexp.\nSee the \\[verilog-faq] for examples on using this." (choice (const nil) regexp) verilog-auto-template-warn-unused "Non-nil means report warning if an AUTO_TEMPLATE line is not used.\nThis feature is not supported before Emacs 21.1 or XEmacs 21.4." verilog-auto-tieoff-declaration "wire" "Data type used for the declaration for AUTOTIEOFF.\nIf \"wire\" then create a wire, if \"assign\" create an\nassignment, else the data type for variable creation." verilog-auto-tieoff-ignore-regexp "If non-nil, when creating AUTOTIEOFF, ignore signals matching this regexp.\nSee the \\[verilog-faq] for examples on using this." (choice (const nil) regexp) verilog-auto-unused-ignore-regexp "If non-nil, when creating AUTOUNUSED, ignore signals matching this regexp.\nSee the \\[verilog-faq] for examples on using this." (choice (const nil) regexp) verilog-case-fold "Non-nil means `verilog-mode' regexps should ignore case.\nThis variable is t for backward compatibility; nil is suggested." "24.4" verilog-mode verilog-typedef-regexp "If non-nil, regular expression that matches Verilog-2001 typedef names.\nFor example, \"_t$\" matches typedefs named with _t, as in the C language.\nSee also `verilog-case-fold'." (choice (const nil) regexp) verilog-mode-hook 'verilog-set-compile-command "Hook run after Verilog mode is loaded." hook verilog-auto-hook "Hook run after `verilog-mode' updates AUTOs." verilog-before-auto-hook "Hook run before `verilog-mode' updates AUTOs." verilog-delete-auto-hook "Hook run after `verilog-mode' deletes AUTOs." verilog-before-delete-auto-hook "Hook run before `verilog-mode' deletes AUTOs." verilog-getopt-flags-hook "Hook run after `verilog-getopt-flags' determines the Verilog option lists." verilog-before-getopt-flags-hook "Hook run before `verilog-getopt-flags' determines the Verilog option lists." verilog-before-save-font-hook "Hook run before `verilog-save-font-no-change-functions' removes highlighting." verilog-after-save-font-hook "Hook run after `verilog-save-font-no-change-functions' restores highlighting."] 10)
#@69 Imenu expression for Verilog mode.  See `imenu-generic-expression'.
(defvar verilog-imenu-generic-expression '((nil "^\\s-*\$?:m\\(?:odule\\|acromodule\$\\|p\$?:rimitive\\|rogram\\|ackage\$\\)\\s-+\$[a-zA-Z0-9_.:]+\$" 1) ("*Variables*" "^\\s-*\$reg\\|wire\\|logic\$\\s-+\$\\|\\[[^]]+\\]\\s-+\$\$[A-Za-z0-9_]+\$" 3) ("*Classes*" "^\\s-*\$?:\\(?:virtual\\|interface\$\\s-+\\)?class\\s-+\$[A-Za-z_][A-Za-z0-9_]+\$" 1) ("*Tasks*" "^\\s-*\$?:\\(?:static\\|pure\\|virtual\\|local\\|protected\$\\s-+\\)*task\\s-+\$?:\\(?:static\\|automatic\$\\s-+\\)?\$[A-Za-z_][A-Za-z0-9_:]+\$" 1) ("*Functions*" "^\\s-*\$?:\\(?:static\\|pure\\|virtual\\|local\\|protected\$\\s-+\\)*function\\s-+\$?:\\(?:static\\|automatic\$\\s-+\\)?\$?:\\w+\\s-+\$?\$?:\\(?:un\$signed\\s-+\\)?\$[A-Za-z_][A-Za-z0-9_:]+\$" 1) ("*Interfaces*" "^\\s-*interface\\s-+\$[a-zA-Z_0-9]+\$" 1) ("*Types*" "^\\s-*typedef\\s-+.*\\s-+\$[a-zA-Z_0-9]+\$\\s-*;" 1)) (#$ . 40746))
#@188 If non-nil, dates are written in scientific format (e.g.  1997/09/17).
If nil, in European format (e.g.  17.09.1997).  The brain-dead American
format (e.g.  09/17/1997) is not supported.
(defvar verilog-date-scientific-format nil (#$ . 41715))
#@78 Default name of Company for Verilog header.
If set will become buffer local.
(defvar verilog-company nil (#$ . 41965))
(make-variable-buffer-local 'verilog-company)
#@78 Default name of Project for Verilog header.
If set will become buffer local.
(defvar verilog-project nil (#$ . 42136))
(make-variable-buffer-local 'verilog-project)
#@30 Keymap used in Verilog mode.
(defvar verilog-mode-map (byte-code "\301 \302\303\304#\210\302\305\306#\210\302\307\310#\210\302\311\312#\210\302\313\314#\210\302\315\316#\210\302\317\320#\210\321\322!\204?�\302\323\324#\210\302\325\326#\210\302\327\330#\210\302\331\332#\210\302\333\334#\210\302\335\336\337!\203^�\337\202_�\340#\210\302\341\336\342!\203n�\342\202o�\343#\210\302\344\345#\210\302\346\347#\210\302\350\351#\210\302\352\353#\210\302\354\355#\210\302\356\357#\210\302\360\361#\210\302\362\363#\210\302\364\365#\210\302\366\367#\210\302\370\371#\210\302\372\373#\210\302\374\375#\210\302\376\377#\210\302\201@�\201A�#\210\302\201B�\201C�#\210\302\201D�\201E�#\210\302\201F�\201G�#\210)\207" [map make-sparse-keymap define-key ";" electric-verilog-semi [(control 59)] electric-verilog-semi-with-comment ":" electric-verilog-colon "`" electric-verilog-tick "	" electric-verilog-tab "
" electric-verilog-terminate-line [backspace] backward-delete-char-untabify boundp delete-key-deletes-forward [delete] delete-char [(meta delete)] kill-word "\202" electric-verilog-backward-sexp "\206" electric-verilog-forward-sexp "\215" electric-verilog-terminate-and-indent "\211" fboundp completion-at-point verilog-complete-word "\277" completion-help-at-point verilog-show-completions "`" verilog-lint-off "*" verilog-delete-auto-star-implicit "?" verilog-diff-auto "" verilog-label-be "	" verilog-pretty-declarations "=" verilog-pretty-expr "" verilog-submit-bug-report "/" verilog-star-comment "" verilog-comment-region "" verilog-uncomment-region "" verilog-goto-defun "" verilog-delete-auto "" verilog-auto "" verilog-auto-save-compile "" verilog-preprocess "" verilog-inject-auto "" verilog-expand-vector "" verilog-header] 5) (#$ . 42307))
#@23 Menu for Verilog mode
(defvar verilog-menu nil (#$ . 44123))
(byte-code "\301\302\303\304\305\306\307\310\311\312\313\314\315\311\316\317\320\321\322\323\324\325\326\327!\203!�\327\202\"�\330\331BB\"\332BBBBBBBBBBBBBBBB!$\207" [verilog-mode-map easy-menu-do-define verilog-menu "Menu for Verilog mode" verilog-easy-menu-filter "Verilog" ("Choose Compilation Action" ["None" (progn (setq verilog-tool nil) (verilog-set-compile-command)) :style radio :selected (equal verilog-tool nil) :help "When invoking compilation, use compile-command"] ["Lint" (progn (setq verilog-tool 'verilog-linter) (verilog-set-compile-command)) :style radio :selected (equal verilog-tool 'verilog-linter) :help "When invoking compilation, use lint checker"] ["Coverage" (progn (setq verilog-tool 'verilog-coverage) (verilog-set-compile-command)) :style radio :selected (equal verilog-tool 'verilog-coverage) :help "When invoking compilation, annotate for coverage"] ["Simulator" (progn (setq verilog-tool 'verilog-simulator) (verilog-set-compile-command)) :style radio :selected (equal verilog-tool 'verilog-simulator) :help "When invoking compilation, interpret Verilog source"] ["Compiler" (progn (setq verilog-tool 'verilog-compiler) (verilog-set-compile-command)) :style radio :selected (equal verilog-tool 'verilog-compiler) :help "When invoking compilation, compile Verilog source"] ["Preprocessor" (progn (setq verilog-tool 'verilog-preprocessor) (verilog-set-compile-command)) :style radio :selected (equal verilog-tool 'verilog-preprocessor) :help "When invoking compilation, preprocess Verilog source, see also `verilog-preprocess'"]) ("Move" ["Beginning of function" verilog-beg-of-defun :keys "C-M-a" :help "Move backward to the beginning of the current function or procedure"] ["End of function" verilog-end-of-defun :keys "C-M-e" :help "Move forward to the end of the current function or procedure"] ["Mark function" verilog-mark-defun :keys "C-M-h" :help "Mark the current Verilog function or procedure"] ["Goto function/module" verilog-goto-defun :help "Move to specified Verilog module/task/function"] ["Move to beginning of block" electric-verilog-backward-sexp :help "Move backward over one balanced expression"] ["Move to end of block" electric-verilog-forward-sexp :help "Move forward over one balanced expression"]) ("Comments" ["Comment Region" verilog-comment-region :help "Put marked area into a comment"] ["UnComment Region" verilog-uncomment-region :help "Uncomment an area commented with Comment Region"] ["Multi-line comment insert" verilog-star-comment :help "Insert Verilog /* */ comment at point"] ["Lint error to comment" verilog-lint-off :help "Convert a Verilog linter warning line into a disable statement"]) "----" ["Compile" compile :help "Perform compilation-action (above) on the current buffer"] ["AUTO, Save, Compile" verilog-auto-save-compile :help "Recompute AUTOs, save buffer, and compile"] ["Next Compile Error" next-error :help "Visit next compilation error message and corresponding source code"] ["Ignore Lint Warning at point" verilog-lint-off :help "Convert a Verilog linter warning line into a disable statement"] ["Line up declarations around point" verilog-pretty-declarations :help "Line up declarations around point"] ["Line up equations around point" verilog-pretty-expr :help "Line up expressions around point"] ["Redo/insert comments on every end" verilog-label-be :help "Label matching begin ... end statements"] ["Expand [x:y] vector line" verilog-expand-vector :help "Take a signal vector on the current line and expand it to multiple lines"] ["Insert begin-end block" verilog-insert-block :help "Insert begin ... end"] apply vector "Complete word" fboundp completion-at-point verilog-complete-word (:help "Complete word at point") ("----" ["Recompute AUTOs" verilog-auto :help "Expand AUTO meta-comment statements"] ["Kill AUTOs" verilog-delete-auto :help "Remove AUTO expansions"] ["Diff AUTOs" verilog-diff-auto :help "Show differences in AUTO expansions"] ["Inject AUTOs" verilog-inject-auto :help "Inject AUTOs into legacy non-AUTO buffer"] ("AUTO Help..." ["AUTO General" (describe-function 'verilog-auto) :help "Help introduction on AUTOs"] ["AUTO Library Flags" (describe-variable 'verilog-library-flags) :help "Help on verilog-library-flags"] ["AUTO Library Path" (describe-variable 'verilog-library-directories) :help "Help on verilog-library-directories"] ["AUTO Library Files" (describe-variable 'verilog-library-files) :help "Help on verilog-library-files"] ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions) :help "Help on verilog-library-extensions"] ["AUTO `define Reading" (describe-function 'verilog-read-defines) :help "Help on reading `defines"] ["AUTO `include Reading" (describe-function 'verilog-read-includes) :help "Help on parsing `includes"] ["AUTOARG" (describe-function 'verilog-auto-arg) :help "Help on AUTOARG - declaring module port list"] ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum) :help "Help on AUTOASCIIENUM - creating ASCII for enumerations"] ["AUTOASSIGNMODPORT" (describe-function 'verilog-auto-assign-modport) :help "Help on AUTOASSIGNMODPORT - creating assignments to/from modports"] ["AUTOINOUT" (describe-function 'verilog-auto-inout) :help "Help on AUTOINOUT - adding inouts from cells"] ["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-comp) :help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"] ["AUTOINOUTIN" (describe-function 'verilog-auto-inout-in) :help "Help on AUTOINOUTIN - copying i/o from another file as all inputs"] ["AUTOINOUTMODPORT" (describe-function 'verilog-auto-inout-modport) :help "Help on AUTOINOUTMODPORT - copying i/o from an interface modport"] ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module) :help "Help on AUTOINOUTMODULE - copying i/o from another file"] ["AUTOINOUTPARAM" (describe-function 'verilog-auto-inout-param) :help "Help on AUTOINOUTPARAM - copying parameters from another file"] ["AUTOINPUT" (describe-function 'verilog-auto-input) :help "Help on AUTOINPUT - adding inputs from cells"] ["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp) :help "Help on AUTOINSERTLISP - insert text from a lisp function"] ["AUTOINSERTLAST" (describe-function 'verilog-auto-insert-last) :help "Help on AUTOINSERTLISPLAST - insert text from a lisp function"] ["AUTOINST" (describe-function 'verilog-auto-inst) :help "Help on AUTOINST - adding pins for cells"] ["AUTOINST (.*)" (describe-function 'verilog-auto-star) :help "Help on expanding Verilog-2001 .* pins"] ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param) :help "Help on AUTOINSTPARAM - adding parameter pins to cells"] ["AUTOLOGIC" (describe-function 'verilog-auto-logic) :help "Help on AUTOLOGIC - declaring logic signals"] ["AUTOOUTPUT" (describe-function 'verilog-auto-output) :help "Help on AUTOOUTPUT - adding outputs from cells"] ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every) :help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"] ["AUTOREG" (describe-function 'verilog-auto-reg) :help "Help on AUTOREG - declaring registers for non-wires"] ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input) :help "Help on AUTOREGINPUT - declaring inputs for non-wires"] ["AUTORESET" (describe-function 'verilog-auto-reset) :help "Help on AUTORESET - resetting always blocks"] ["AUTOSENSE or AS" (describe-function 'verilog-auto-sense) :help "Help on AUTOSENSE - sensitivity lists for always blocks"] ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff) :help "Help on AUTOTIEOFF - tying off unused outputs"] ["AUTOUNDEF" (describe-function 'verilog-auto-undef) :help "Help on AUTOUNDEF - undefine all local defines"] ["AUTOUNUSED" (describe-function 'verilog-auto-unused) :help "Help on AUTOUNUSED - terminating unused inputs"] ["AUTOWIRE" (describe-function 'verilog-auto-wire) :help "Help on AUTOWIRE - declaring wires for cells"]) "----" ["Submit bug report" verilog-submit-bug-report :help "Submit via mail a bug report on verilog-mode.el"] ["Version and FAQ" verilog-faq :help "Show the current version, and where to get the FAQ etc"] ["Customize Verilog Mode..." verilog-customize :help "Customize variables and other settings used by Verilog-Mode"] ["Customize Verilog Fonts & Colors" verilog-font-customize :help "Customize fonts used by Verilog-Mode."])] 25)
#@42 Menu for statement templates in Verilog.
(defvar verilog-stmt-menu nil (#$ . 52509))
(byte-code "\301\302\303\304\305!$\207" [verilog-mode-map easy-menu-do-define verilog-stmt-menu "Menu for statement templates in Verilog." verilog-easy-menu-filter ("Statements" ["Header" verilog-sk-header :help "Insert a header block at the top of file"] ["Comment" verilog-sk-comment :help "Insert a comment block"] "----" ["Module" verilog-sk-module :help "Insert a module .. (/*AUTOARG*/);.. endmodule block"] ["OVM Class" verilog-sk-ovm-class :help "Insert an OVM class block"] ["UVM Object" verilog-sk-uvm-object :help "Insert an UVM object block"] ["UVM Component" verilog-sk-uvm-component :help "Insert an UVM component block"] ["Primitive" verilog-sk-primitive :help "Insert a primitive .. (.. );.. endprimitive block"] "----" ["Input" verilog-sk-input :help "Insert an input declaration"] ["Output" verilog-sk-output :help "Insert an output declaration"] ["Inout" verilog-sk-inout :help "Insert an inout declaration"] ["Wire" verilog-sk-wire :help "Insert a wire declaration"] ["Reg" verilog-sk-reg :help "Insert a register declaration"] ["Define thing under point as a register" verilog-sk-define-signal :help "Define signal under point as a register at the top of the module"] "----" ["Initial" verilog-sk-initial :help "Insert an initial begin .. end block"] ["Always" verilog-sk-always :help "Insert an always @(AS) begin .. end block"] ["Function" verilog-sk-function :help "Insert a function .. begin .. end endfunction block"] ["Task" verilog-sk-task :help "Insert a task .. begin .. end endtask block"] ["Specify" verilog-sk-specify :help "Insert a specify .. endspecify block"] ["Generate" verilog-sk-generate :help "Insert a generate .. endgenerate block"] "----" ["Begin" verilog-sk-begin :help "Insert a begin .. end block"] ["If" verilog-sk-if :help "Insert an if (..) begin .. end block"] ["(if) else" verilog-sk-else-if :help "Insert an else if (..) begin .. end block"] ["For" verilog-sk-for :help "Insert a for (...) begin .. end block"] ["While" verilog-sk-while :help "Insert a while (...) begin .. end block"] ["Fork" verilog-sk-fork :help "Insert a fork begin .. end .. join block"] ["Repeat" verilog-sk-repeat :help "Insert a repeat (..) begin .. end block"] ["Case" verilog-sk-case :help "Insert a case block, prompting for details"] ["Casex" verilog-sk-casex :help "Insert a casex (...) item: begin.. end endcase block"] ["Casez" verilog-sk-casez :help "Insert a casez (...) item: begin.. end endcase block"])] 6)
#@46 Abbrev table in use in Verilog-mode buffers.
(defvar verilog-mode-abbrev-table nil (#$ . 55049))
(byte-code "\301\300\302\303\304\305\306\307&\210\310\311\312\313$\210\310\314\312\315$\210\310\316\302\317$\210\310\320\312\321$\210\310\322\312\323$\210\310\324\312\325$\210\310\326\312\327$\210\310\330\312\331$\210\310\332\312\333$\210\310\334\312\335$\210\310\336\312\337$\210\310\340\312\341$\210\310\342\312\343$\210\310\344\312\345$\210\310\346\312\347$\210\310\350\312\351$\210\310\352\312\353$\210\310\354\312\355$\210\310\356\312\357$\210\310\360\312\361$\210\310\362\312\363$\210\310\364\312\365$\210\310\366\312\367$\210\310\370\312\371$\210\310\372\312\373$\207" [verilog-mode-abbrev-table verilog-define-abbrev-table nil "Abbrev table for Verilog mode skeletons." :case-fixed t :enable-function #[nil "\300 ?\207" [verilog-in-comment-or-string-p] 1] verilog-define-abbrev "class" "" verilog-sk-ovm-class "always" verilog-sk-always "begin" verilog-sk-begin "case" verilog-sk-case "for" verilog-sk-for "generate" verilog-sk-generate "initial" verilog-sk-initial "fork" verilog-sk-fork "module" verilog-sk-module "primitive" verilog-sk-primitive "repeat" verilog-sk-repeat "specify" verilog-sk-specify "task" verilog-sk-task "while" verilog-sk-while "casex" verilog-sk-casex "casez" verilog-sk-casez "if" verilog-sk-if "else if" verilog-sk-else-if "assign" verilog-sk-assign "function" verilog-sk-function "input" verilog-sk-input "output" verilog-sk-output "inout" verilog-sk-inout "wire" verilog-sk-wire "reg" verilog-sk-reg] 8)
(defalias 'verilog-within-string #[nil "\300\301\302 `\"8\207" [3 parse-partial-sexp line-beginning-position] 4])
(put 'verilog-within-string 'byte-optimizer 'byte-compile-inline-expand)
#@244 Like `string-match', but use `verilog-case-fold'.
Return index of start of first match for REGEXP in STRING, or nil.
Matching ignores case if `verilog-case-fold' is non-nil.
If third arg START is non-nil, start search at that index in STRING.
(defalias 'verilog-string-match-fold #[(regexp string &optional start) "\305\n\f#)\207" [verilog-case-fold case-fold-search regexp string start string-match] 4 (#$ . 56808)])
(put 'verilog-string-match-fold 'byte-optimizer 'byte-compile-inline-expand)
#@264 Replace occurrences of FROM-STRING with TO-STRING.
FIXEDCASE and LITERAL as in `replace-match'.  STRING is what to replace.
The case (verilog-string-replace-matches "o" "oo" nil nil "foobar")
will break, as the o's continuously replace.  xa -> x works ok though.
(defalias 'verilog-string-replace-matches #[(from-string to-string fixedcase literal string) "\306\307	\n#\203�\310\f
\n$\211G\306\224G\\^\202�\n)\207" [start from-string string to-string fixedcase literal 0 string-match replace-match] 6 (#$ . 57313)])
(put 'verilog-string-replace-matches 'byte-optimizer 'byte-compile-inline-expand)
#@35 Remove spaces surrounding STRING.
(defalias 'verilog-string-remove-spaces #[(string) "\306 \307\216\310\311\312\211	\313\314
	#\203/�\315\f\n	$\211G\313\224\fG\\^\202�	.\316\311\312\211	\313\314
	#\203]�\315\f\n	$\211G\313\224\fG\\^\202@�	.\211*\207" [save-match-data-internal string literal fixedcase to-string from-string match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] "^\\s-+" "" nil 0 string-match replace-match "\\s-+$" start] 6 (#$ . 57925)])
(put 'verilog-string-remove-spaces 'byte-optimizer 'byte-compile-inline-expand)
#@72 Like `re-search-forward', but skips over match in comments or strings.
(defalias 'verilog-re-search-forward #[(REGEXP BOUND NOERROR) "\304\305	\n#\203&�\306 \211\203&�\307 \203&�\310\n\203\"�`\nW\202#�\311\204�\312!\210\313\225)\207" [mdata REGEXP BOUND NOERROR (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) t store-match-data 0] 4 (#$ . 58535)])
(put 'verilog-re-search-forward 'byte-optimizer 'byte-compile-inline-expand)
#@73 Like `re-search-backward', but skips over match in comments or strings.
(defalias 'verilog-re-search-backward #[(REGEXP BOUND NOERROR) "\304\305	\n#\203&�\306 \211\203&�\307 \203&�\310\n\203\"�`\nV\202#�\311\204�\312!\210\313\225)\207" [mdata REGEXP BOUND NOERROR (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0] 4 (#$ . 59013)])
(put 'verilog-re-search-backward 'byte-optimizer 'byte-compile-inline-expand)
#@280 Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
but trashes match data and is faster for REGEXP that doesn't match often.
This uses `verilog-scan' and text properties to ignore comments,
so there may be a large up front penalty for the first search.
(defalias 'verilog-re-search-forward-quick #[(regexp bound noerror) "\304\204%�\305	\n#\203%�\306\307\224!\203�\305\310\304\311#\210\202�\307\225\211\203�)\207" [pt regexp bound noerror nil re-search-forward verilog-inside-comment-or-string-p 0 "[/\"\n]" t] 5 (#$ . 59497)])
(put 'verilog-re-search-forward-quick 'byte-optimizer 'byte-compile-inline-expand)
#@281 Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
but trashes match data and is faster for REGEXP that doesn't match often.
This uses `verilog-scan' and text properties to ignore comments,
so there may be a large up front penalty for the first search.
(defalias 'verilog-re-search-backward-quick #[(regexp bound noerror) "\304\204%�\305	\n#\203%�\306\307\224!\203�\305\310\304\311#\210\202�\307\224\211\203�)\207" [pt regexp bound noerror nil re-search-backward verilog-inside-comment-or-string-p 0 "[/\"]" t] 5 (#$ . 60149)])
(put 'verilog-re-search-backward-quick 'byte-optimizer 'byte-compile-inline-expand)
#@242 Like `re-search-forward', but first search for SUBSTR constant.
Then searched for the normal REGEXP (which contains SUBSTR), with given
BOUND and NOERROR.  The REGEXP must fit within a single line.
This speeds up complicated regexp matches.
(defalias 'verilog-re-search-forward-substr #[(substr regexp bound noerror) "\305\204.�\306	\n#\203.�\212\307 \210\310\f\311 #)\312\224`X\203(�\312\225`Y\204�\305\211\203�\2035�b\210)\207" [done substr bound noerror regexp nil search-forward beginning-of-line re-search-forward line-end-position 0] 5 (#$ . 60803)])
(put 'verilog-re-search-forward-substr 'byte-optimizer 'byte-compile-inline-expand)
#@243 Like `re-search-backward', but first search for SUBSTR constant.
Then searched for the normal REGEXP (which contains SUBSTR), with given
BOUND and NOERROR.  The REGEXP must fit within a single line.
This speeds up complicated regexp matches.
(defalias 'verilog-re-search-backward-substr #[(substr regexp bound noerror) "\305\204.�\306	\n#\203.�\212\305\210\307\f\310 #)\311\224`X\203(�\311\225`Y\204�\305\211\203�\2035�b\210)\207" [done substr bound noerror regexp nil search-backward re-search-backward line-beginning-position 0] 5 (#$ . 61462)])
(put 'verilog-re-search-backward-substr 'byte-optimizer 'byte-compile-inline-expand)
#@242 Delete trailing spaces or tabs, but not newlines nor linefeeds.
Also add missing final newline.

To call this from the command line, see \[verilog-batch-diff-auto].

To call on \[verilog-auto], set `verilog-auto-delete-trailing-whitespace'.
(defalias 'verilog-delete-trailing-whitespace #[nil "\212eb\210\300\301\302\303#\203�\304\305\302\211#\210\202�db\210n?\205�\306c)\207" [re-search-forward "[ 	]+$" nil t replace-match "" "\n"] 4 (#$ . 62114)])
#@1088 Function to compute shell command to compile Verilog.

This reads `verilog-tool' and sets `compile-command'.  This specifies the
program that executes when you type \[compile] or
\[verilog-auto-save-compile].

By default `verilog-tool' uses a Makefile if one exists in the
current directory.  If not, it is set to the `verilog-linter',
`verilog-compiler', `verilog-coverage', `verilog-preprocessor',
or `verilog-simulator' variables, as selected with the Verilog ->
"Choose Compilation Action" menu.

You should set `verilog-tool' or the other variables to the path and
arguments for your Verilog simulator.  For example:
    "vcs -p123 -O"
or a string like:
    "(cd /tmp; surecov %s)".

In the former case, the path to the current buffer is concat'ed to the
value of `verilog-tool'; in the later, the path to the current buffer is
substituted for the %s.

Where __FLAGS__ appears in the string `verilog-current-flags'
will be substituted.

Where __FILE__ appears in the string, the variable
`buffer-file-name' of the current buffer, without the directory
portion, will be substituted.
(defalias 'verilog-set-compile-command #[nil "\303\304!\204\f�\303\305!\203�\306\300!\210\307\202B�\306\300!\210	\203@�\310\311\312	!\"\2033�\313\312	!\n\206/�\314\"\202A�\312	!\315\n\206<�\314Q\202A�\314\316 \207" [compile-command verilog-tool buffer-file-name file-exists-p "makefile" "Makefile" make-local-variable "make " string-match "%s" eval format "" " " verilog-modify-compile-command] 4 (#$ . 62576) nil])
#@258 Replace meta-information in COMMAND and return it.
Where __FLAGS__ appears in the string `verilog-current-flags'
will be substituted.  Where __FILE__ appears in the string, the
current buffer's file-name, without the directory portion, will
be substituted.
(defalias 'verilog-expand-command #[(command) "\306\307 \310\211\311\312
	#\203+�\313\f\n	$\211G\311\224\fG\\^\202�	.\314\315\316 \2067�\317!\310\211\311\312
	#\203`�\313\f\n	$\211G\311\224\fG\\^\202C�	.\211\207" [command string literal fixedcase to-string from-string "\\b__FLAGS__\\b" verilog-current-flags t 0 string-match replace-match "\\b__FILE__\\b" file-name-nondirectory buffer-file-name "" start] 6 (#$ . 64089)])
#@58 Update `compile-command' using `verilog-expand-command'.
(defalias 'verilog-modify-compile-command #[nil ";\205/�\303\301!\203�	\232\203�\n\304\305\"\205/�\306\302!\210\306\300!\210\307!\306\301!\210\211\207" [compile-command verilog-compile-command-post-mod verilog-compile-command-pre-mod boundp string-match "\\b\$__FLAGS__\\|__FILE__\$\\b" make-local-variable verilog-expand-command] 3 (#$ . 64809)])
#@123 Tell Emacs compile that we are Verilog.
Called by `compilation-mode-hook'.  This allows \[next-error] to
find the errors.
(defalias 'verilog-error-regexp-add-emacs #[nil "\302\300!\205�\303\304\"?\205�\305\306	\"\207" [compilation-error-regexp-alist-alist verilog-error-regexp-emacs-alist boundp assoc verilog-xl-1 mapcar #[(item) "@	B\nB\211\207" [item compilation-error-regexp-alist compilation-error-regexp-alist-alist] 2]] 3 (#$ . 65235) nil])
(add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs)
#@38 List of Verilog compiler directives.
(defconst verilog-compiler-directives '("`__FILE__" "`__LINE" "`begin_keywords" "`celldefine" "`default_nettype" "`define" "`else" "`elsif" "`end_keywords" "`endcelldefine" "`endif" "`ifdef" "`ifndef" "`include" "`line" "`nounconnected_drive" "`pragma" "`resetall" "`timescale" "`unconnected_drive" "`undef" "`undefineall" "`case" "`default" "`endfor" "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`let" "`protect" "`switch" "`time_scale" "`uselib" "`while") (#$ . 65762))
(defconst verilog-directive-re (verilog-regexp-words verilog-compiler-directives))
(defconst verilog-directive-re-1 (concat "[ 	]*" verilog-directive-re))
(defconst verilog-directive-begin "\\<`\$for\\|i\\(f\\|fdef\\|fndef\$\\|switch\\|while\\)\\>")
(defconst verilog-directive-middle "\\<`\$else\\|elsif\\|default\\|case\$\\>")
(defconst verilog-directive-end "`\$endfor\\|endif\\|endswitch\\|endwhile\$\\>")
(defconst verilog-ovm-begin-re "\$?:`ovm_\\(?:\\(?:component\\(?:_param\$?\\|field\\|object\$?:_param\$?\\|sequencer?\\)_utils_begin\\)\\)")
(defconst verilog-ovm-end-re "\$?:`ovm_\\(?:\\(?:component\\|field\\|object\\|sequencer?\$_utils_end\\)\\)")
(defconst verilog-uvm-begin-re "\$?:`uvm_\\(?:\\(?:component\\(?:_param\$?\\|field\\|object\$?:_param\$?\\|sequencer?\\)_utils_begin\\)\\)")
(defconst verilog-uvm-end-re "\$?:`uvm_\\(?:\\(?:component\\|field\\|object\\|sequencer?\$_utils_end\\)\\)")
(defconst verilog-vmm-begin-re "\$?:`vmm_\\(?:\\(?:data\\|env\\|s\\(?:cenario\\|ubenv\$\\|xactor\\)_member_begin\\)\\)")
(defconst verilog-vmm-end-re "\$?:`vmm_\\(?:\\(?:data\\|env\\|s\\(?:cenario\\|ubenv\$\\|xactor\\)_member_end\\)\\)")
(defconst verilog-vmm-statement-re "`vmm_\$data\\|env\\|scenario\\|subenv\\|xactor\$_member_\$scalar\\|string\\|enum\\|vmm_data\\|channel\\|xactor\\|subenv\\|user_defined\$\$_array\$?")
(defconst verilog-ovm-statement-re "\$?:`\\(?:DUT_ERROR\\|MESSAGE\\|dut_error\\|message\\|ovm_\\(?:analysis_imp_decl\\|blocking_\\(?:\\(?:get\\(?:_peek\$?\\|master\\|p\$?:eek\\|ut\$\\|slave\\|transport\\)_imp_decl\\)\\|c\$?:omponent_\\(?:registry\\(?:_param\$?\\|utils\\)\\|reate\$?:_seq\$?\\)\\|d\$?:eclare_sequence_lib\\|o\\(?:_\\(?:seq\\(?:_with\$?\\|with\\)\\)?\\)\\|error\\|f\$?:atal\\|i\\(?:eld_\\(?:a\\(?:a_\\(?:int_\\(?:byte\\(?:_unsigned\$?\\|int\$?:_unsigned\\|eger\\(?:_unsigned\$?\\)?\\|key\\|longint\$?:_unsigned\$?\\|s\$?:hortint\\(?:_unsigned\$?\\|tring\\)\\)\\|object_\$?:int\\|string\$\\|string_\$?:int\\|string\$\\)\\|rray_\$?:int\\|object\\|string\$\\)\\|e\$?:num\\|vent\$\\|int\\|object\\|queue_\$?:int\\|object\\|string\$\\|s\$?:array_int\\|tring\$\\|utils\\)\\|le\\)\\)\\|get_\$?:\\(?:peek_\$?imp_decl\\)\\|info[1-4]?\\|line\\|m\$?:\\(?:aster_imp_dec\\|sg_detai\$l\\)\\|non\$?:\\(?:_blocking_transport\\|blocking_\\(?:get\\(?:_peek\$?\\|master\\|p\$?:eek\\|ut\$\\|slave\\)\\)_imp_decl\\)\\|object_\$?:registry\\(?:_param\$?\\|utils\\)\\|p\$?:eek_imp_decl\\|hase_\\(?:\\(?:func\\|task\$_decl\\)\\|rint_\$?:a\\(?:a_\\(?:int_object\\|string_\\(?:int\\|object\\|string\$\\)\\|rray_\$?:int\\|object\\|string\$\\)\\|object_queue\\|queue_int\\|string_queue\\)\\|ut_imp_decl\\)\\|rand_send\$?:_with\$?\\|s\$?:e\\(?:nd\\|quence_utils\$\\|lave_imp_decl\\)\\|transport_imp_decl\\|update_sequence_lib\$?:_and_item\$?\\|warning\\)\\|static_\$?:dut_error\\|message\$\\)\\)")
(defconst verilog-uvm-statement-re "\$?:`uvm_\\(?:analysis_imp_decl\\|blocking_\\(?:\\(?:get\\(?:_peek\$?\\|master\\|p\$?:eek\\|ut\$\\|slave\\|transport\\)_imp_decl\\)\\|c\$?:omponent_\\(?:param_utils\\|registry\\(?:_param\$?\\|utils\\)\\|reate\$?:_\\(?:on\\|seq\$\\)?\\)\\|d\$?:eclare_\\(?:p_sequencer\\|sequence_lib\$\\|o\$?:_\\(?:callbacks\\(?:_exit_on\$?\\|o\$?:bj_callbacks\\(?:_exit_on\$?\\|n\$?:_\\(?:pri\\(?:_with\$?\\|with\\)\\)?\\)\\|pri\$?:_with\$?\\|seq\$?:_with\$?\\|with\\)\\)?\\)\\|error\$?:_context\$?\\|f\$?:atal\\(?:_context\$?\\|i\$?:eld_\\(?:a\\(?:a_\\(?:int_\\(?:byte\\(?:_unsigned\$?\\|enum\\|int\$?:_unsigned\\|eger\\(?:_unsigned\$?\\)?\\|key\\|longint\$?:_unsigned\$?\\|s\$?:hortint\\(?:_unsigned\$?\\|tring\\)\\)\\|object_\$?:int\\|string\$\\|string_\$?:int\\|string\$\\)\\|rray_\$?:enum\\|int\\|object\\|string\$\\)\\|e\$?:num\\|vent\$\\|int\\|object\\|queue_\$?:enum\\|int\\|object\\|string\$\\|real\\|s\$?:array_\\(?:enum\\|int\\|object\\|string\$\\|tring\\)\\|utils\\)\\|le\\)\\)\\|get_\$?:\\(?:peek_\$?imp_decl\\)\\|info\$?:_context\$?\\|line\\|master_imp_decl\\|non\$?:\\(?:_blocking_transport\\|blocking_\\(?:get\\(?:_peek\$?\\|master\\|p\$?:eek\\|ut\$\\|slave\\|transport\\)\\)_imp_decl\\)\\|object_\$?:param_utils\\|registry\\(?:_param\$?\\|utils\\)\\|p\$?:ack_\\(?:arrayN?\\|enumN?\\|intN?\\|queueN?\\|real\\|s\\(?:arrayN?\\|tring\$\\)\\|\$?:eek\\|ut\$_imp_decl\\)\\|r\$?:and_send\\(?:_\\(?:pri\\(?:_with\$?\\|with\\)\\)?\\|e\$?:cord_\\(?:attribute\\|field\$\\|gister_cb\\)\\)\\|s\$?:e\\(?:nd\\(?:_pri\$?\\|quence_utils\\|t_super_type\\)\\|lave_imp_decl\\)\\|transport_imp_decl\\|u\$?:npack_\\(?:arrayN?\\|enumN?\\|intN?\\|queueN?\\|real\\|s\\(?:arrayN?\\|tring\$\\)\\|pdate_sequence_lib\$?:_and_item\$?\\)\\|warning\$?:_context\$?\\)\\)")
(defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
(defconst verilog-assignment-operator-re "\$!=[=?]?\\|#\\(?:[=-]#\$\\|%=\\|&=\\|\\*=\\|\\+=\\|-\$?:>>\\|[=>]\$\\|/=\\|:[/=]\\|<\$?:->\\|\\(?:<<?\$?=\\)\\|=\$?:=[=?]?\$?\\|>\$?:\\(?:>>?\$?=\\)\\|\\^=\\||\$?:->\\|=>?\$\\)")
(defconst verilog-assignment-operation-re (concat "\$^.*?\$\\B" verilog-assignment-operator-re "\\B"))
(defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
(defconst verilog-property-re (concat "\$" verilog-label-re "\$?\$\\(assert\\|assume\\|cover\$\\>\\s-+\\<property\\>\\)\\|\$assert\$"))
(defconst verilog-no-indent-begin-re "\\<\$always\\(?:_\\(?:comb\\|ff\\|latch\$\\)?\\|do\\|else\\|f\$?:inal\\|or\\(?:e\\(?:ach\\|ver\$\\)?\\)\\|i\$?:f\\|nitial\$\\|repeat\\|while\\)\\>")
(defconst verilog-ends-re "\$\\<else\\>\$\\|\$\\<if\\>\$\\|\$\\<assert\\>\$\\|\$\\<end\\>\$\\|\$\\<endcase\\>\$\\|\$\\<endfunction\\>\$\\|\$\\<endtask\\>\$\\|\$\\<endspecify\\>\$\\|\$\\<endtable\\>\$\\|\$\\<endgenerate\\>\$\\|\$\\<join\\(_any\\|_none\$?\\>\\)\\|\$\\<endclass\\>\$\\|\$\\<endgroup\\>\$\\|\$\\<`vmm_data_member_end\\>\$\\|\$\\<`vmm_env_member_end\\>\$\\|\$\\<`vmm_scenario_member_end\\>\$\\|\$\\<`vmm_subenv_member_end\\>\$\\|\$\\<`vmm_xactor_member_end\\>\$\\|\$\\<`ovm_component_utils_end\\>\$\\|\$\\<`ovm_field_utils_end\\>\$\\|\$\\<`ovm_object_utils_end\\>\$\\|\$\\<`ovm_sequence_utils_end\\>\$\\|\$\\<`ovm_sequencer_utils_end\\>\$\$\\<`uvm_component_utils_end\\>\$\\|\$\\<`uvm_field_utils_end\\>\$\\|\$\\<`uvm_object_utils_end\\>\$\\|\$\\<`uvm_sequence_utils_end\\>\$\\|\$\\<`uvm_sequencer_utils_end\\>\$")
(defconst verilog-auto-end-comment-lines-re (concat "\$" verilog-directive-re "\$\\|\$\\<\\(begin\\|e\\(?:lse\\|nd\\(?:c\\(?:ase\\|l\\(?:ass\\|ocking\$\\)\\|function\\|group\\|interface\\|module\\|p\$?:ackage\\|r\\(?:imitive\\|o\\(?:gram\\|perty\$\\)\\)\\|s\$?:equence\\|pecify\$\\|ta\$?:ble\\|sk\$\\)?\\)\\|interface\\|join\$?:_\\(?:any\\|none\$\\)?\\|\$?:m\\(?:\\(?:acrom\$?odul\\)\\|p\$?:ackag\\|rimitiv\$\\)e\\)\\>\\)"))
(defconst verilog-end-block-ordered-re "\$\\<endcase\\>\$\\|\$\\<end\\>\$\\|\$\\<end\\(\\(function\$\\|\$task\$\\|\$module\$\\|\$primitive\$\\|\$interface\$\\|\$package\$\\|\$class\$\\|\$group\$\\|\$program\$\\|\$sequence\$\\|\$clocking\$\\|\$property\$\\|\\)\\>\\)")
(defconst verilog-end-block-re "\\<\$`\\(?:\\(?:ovm_\\(?:\\(?:component\\|field\\|object\\|sequencer?\$_utils\\)\\|uvm_\$?:\\(?:component\\|field\\|object\\|sequencer?\$_utils\\)\\|vmm_\$?:\\(?:data\\|env\\|s\\(?:cenario\\|ubenv\$\\|xactor\\)_member\\)\\)_end\\)\\|end\$?:c\\(?:ase\\|l\\(?:ass\\|ocking\$\\)\\|function\\|g\$?:enerate\\|roup\$\\|interface\\|p\$?:ackage\\|ro\\(?:gram\\|perty\$\\)\\|s\$?:equence\\|pecify\$\\|ta\$?:ble\\|sk\$\\)?\\|join\$?:_\\(?:any\\|none\$\\)?\\)\\>")
(defconst verilog-endcomment-reason-re (concat "\$\\<begin\\>\$\\|\$\\<else\\>\$\\|\$\\<end\\>\\s-+\\<else\\>\$\\|\$\\<always\\(?:_ff\$?\\>\$?:[ 	]*@\$\\)\\|\$\\<always\\(?:_comb\\|_latch\$?\\>\\)\\|\$\\<fork\\>\$\\|\$\\<if\\>\$\\|" verilog-property-re "\\|\$\\(" verilog-label-re "\$?\\<assert\\>\\)\\|\$\\<clocking\\>\$\\|\$\\<task\\>\$\\|\$\\<function\\>\$\\|\$\\<initial\\>\$\\|\$\\<interface\\>\$\\|\$\\<package\\>\$\\|\$\\<final\\>\$\\|\$@\$\\|\$\\<while\\>\$\\|\$\\<do\\>\$\\|\$\\<for\\(ever\\|each\$?\\>\\)\\|\$\\<repeat\\>\$\\|\$\\<wait\\>\$\\|#"))
(defconst verilog-named-block-re "begin[ 	]*:")
(defconst verilog-beg-block-re "\\<\$`\\(?:\\(?:ovm_\\(?:\\(?:component\\(?:_param\$?\\|field\\|object\$?:_param\$?\\|sequencer?\\)_utils\\)\\|uvm_\$?:\\(?:component\\(?:_param\$?\\|field\\|object\$?:_param\$?\\|sequencer?\\)_utils\\)\\|vmm_\$?:\\(?:data\\|env\\|s\\(?:cenario\\|ubenv\$\\|xactor\\)_member\\)\\)_begin\\)\\|begin\\|c\$?:ase[xz]?\\|locking\$\\|f\$?:ork\\|unction\$\\|generate\\|property\\|randcase\\|specify\\|ta\$?:ble\\|sk\$\\)\\>")
(defconst verilog-beg-block-re-ordered "\$\\<begin\\>\$\\|\$\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\$?case[xz]?\\>\\)\\|\$\\(\\<disable\\>\\s-+\\|\\<wait\\>\\s-+\$?fork\\>\\)\\|\$\\<class\\>\$\\|\$\\<table\\>\$\\|\$\\<specify\\>\$\\|\$\\<function\\>\$\\|\$\\(?:\\<\\(?:virtual\\|protected\\|static\$\\>\\s-+\\)*\\<function\\>\\)\\|\$\\<task\\>\$\\|\$\\(?:\\<\\(?:virtual\\|protected\\|static\$\\>\\s-+\\)*\\<task\\>\\)\\|\$\\<generate\\>\$\\|\$\\<covergroup\\>\$\\|\$\\(?:\\(?:\\<cover\\>\\s-+\$\\|\$?:\\<assert\\>\\s-+\$\\)*\\<property\\>\\)\\|\$\\<\\(?:rand\$?sequence\\>\\)\\|\$\\<clocking\\>\$\\|\$\\<`[ou]vm_[a-z_]+_begin\\>\$\\|\$\\<`vmm_[a-z_]+_member_begin\\>\$")
(defconst verilog-end-block-ordered-rry ["\$\\<begin\\>\$\\|\$\\<end\\>\$\\|\$\\<endcase\\>\$\\|\$\\<join\\(_any\\|_none\$?\\>\\)" "\$\\<randcase\\>\\|\\<case[xz]?\\>\$\\|\$\\<endcase\\>\$" "\$\\<fork\\>\$\\|\$\\<join\\(_any\\|_none\$?\\>\\)" "\$\\<class\\>\$\\|\$\\<endclass\\>\$" "\$\\<table\\>\$\\|\$\\<endtable\\>\$" "\$\\<specify\\>\$\\|\$\\<endspecify\\>\$" "\$\\<function\\>\$\\|\$\\<endfunction\\>\$" "\$\\<generate\\>\$\\|\$\\<endgenerate\\>\$" "\$\\<task\\>\$\\|\$\\<endtask\\>\$" "\$\\<covergroup\\>\$\\|\$\\<endgroup\\>\$" "\$\\<property\\>\$\\|\$\\<endproperty\\>\$" "\$\\<\\(rand\$?sequence\\>\\)\\|\$\\<endsequence\\>\$" "\$\\<clocking\\>\$\\|\$\\<endclocking\\>\$"])
(defconst verilog-nameable-item-re "\\<\$begin\\|end\\(?:c\\(?:ase\\|hecker\\|l\\(?:ass\\|ocking\$\\|onfig\\)\\|function\\|g\$?:enerate\\|roup\$\\|interface\\|module\\|p\$?:ackage\\|r\\(?:imitive\\|o\\(?:gram\\|perty\$\\)\\)\\|s\$?:equence\\|pecify\$\\|ta\$?:ble\\|sk\$\\)?\\|fork\\|join\$?:_\\(?:any\\|none\$\\)?\\)\\>")
(defconst verilog-declaration-opener "\\<\$begin\\|function\\|module\\|task\$\\>")
(defconst verilog-declaration-prefix-re "\\<\$const\\|in\\(?:[op]ut\$\\|local\$?:param\$?\\|output\\|p\$?:arameter\\|rotected\$\\|r\$?:and\\|ef\$\\|static\\|typedef\\|var\\)\\>")
(defconst verilog-declaration-core-re "\\<\$b\\(?:it\\|yte\$\\|chandle\\|e\$?:num\\|vent\$\\|genvar\\|in\$?:out\\|put\\|t\\(?:eger\$?\\)\\|lo\$?:gic\\|ngint\$\\|mailbox\\|output\\|re\$?:al\\(?:time\$?\\|g\\)\\|s\$?:emaphore\\|hort\\(?:int\\|real\$\\|tr\$?:ing\\|uct\$\\|upply[01]\\)\\|t\$?:ime\\|ri\\(?:and\\|or\\|reg\\|[01]\$?\\)\\|u\$?:nion\\|wire\$\\|virtual\\|w\$?:and\\|ire\\|or\$\\)\\>")
(defconst verilog-declaration-re (concat "\$" verilog-declaration-prefix-re "\\s-*\$?" verilog-declaration-core-re))
(defconst verilog-range-re "\$\\[[^]]*\\]\\s-*\$+")
(defconst verilog-optional-signed-re "\\s-*\$\\(un\$?signed\\)?")
(defconst verilog-optional-signed-range-re (concat "\\s-*\$\\<\\(reg\\|wire\$\\>\\s-*\\)?\$\\<\\(un\$?signed\\>\\s-*\\)?\$" verilog-range-re "\$?"))
(defconst verilog-macroexp-re "`\\sw+")
(defconst verilog-delay-re "#\\s-*\$\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\$?\\)\\|\$([^()]*)\$\\|\$\\sw+\$\\)")
(defconst verilog-declaration-re-2-no-macro (concat "\\s-*" verilog-declaration-re "\\s-*\$\\(" verilog-optional-signed-range-re "\$\\|\$" verilog-delay-re "\$\\)"))
(defconst verilog-declaration-re-2-macro (concat "\\s-*" verilog-declaration-re "\\s-*\$\\(" verilog-optional-signed-range-re #1="\$\\|\$" verilog-delay-re #1# verilog-macroexp-re "\$\\)"))
(defconst verilog-declaration-re-1-macro (concat "^" verilog-declaration-re-2-macro))
(defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
(defconst verilog-defun-re "\\<\$c\\(?:lass\\|onfig\$\\|interface\\|m\$?:\\(?:acrom\$?odule\\)\\|p\$?:ackage\\|r\\(?:imitive\\|ogram\$\\)\\)\\>")
(defconst verilog-end-defun-re "\\<\$end\\(?:c\\(?:lass\\|onfig\$\\|interface\\|module\\|p\$?:ackage\\|r\\(?:imitive\\|ogram\$\\)\\)\\)\\>")
(defconst verilog-zero-indent-re (concat verilog-defun-re "\\|" verilog-end-defun-re))
(defconst verilog-inst-comment-re "\\<\$In\\(?:outs\\|puts\\|terface[ds]\$\\|Outputs\\)\\>")
(defconst verilog-behavioral-block-beg-re "\\<\$always\\(?:_\\(?:comb\\|ff\\|latch\$\\)?\\|f\$?:inal\\|unction\$\\|initial\\|task\\)\\>")
(defconst verilog-coverpoint-re "\\w+\\s-*:\\s-*\$coverpoint\\|cross\\|constraint\$")
(defconst verilog-in-constraint-re "\\<\$else\\|foreach\\|if\\|solve\$\\>")
(defconst verilog-indent-re "\\<\$`\\(?:case\\|def\\(?:ault\\|ine\$\\|e\$?:ls\\(?:e\\|if\$\\|nd\$?:for\\|if\\|protect\\|switch\\|while\$\\)\\|for\$?:mat\$?\\|i\$?:f\\(?:n?def\$?\\|nclude\\)\\|let\\|ovm_\$?:component_\\(?:param_utils_begin\\|utils_\\(?:begin\\|end\$\\)\\|field_utils_\$?:begin\\|end\$\\|object_\$?:param_utils_begin\\|utils_\\(?:begin\\|end\$\\)\\|sequence\$?:_utils_\\(?:begin\\|end\$\\|r_utils_\$?:begin\\|end\$\\)\\)\\|protect\\|switch\\|time\$?:_?scale\$\\|u\$?:ndef\\|vm_\\(?:component_\\(?:param_utils_begin\\|utils_\\(?:begin\\|end\$\\)\\|field_utils_\$?:begin\\|end\$\\|object_\$?:param_utils_begin\\|utils_\\(?:begin\\|end\$\\)\\|sequence\$?:_utils_\\(?:begin\\|end\$\\|r_utils_\$?:begin\\|end\$\\)\\)\\)\\|vmm_\$?:data_member_\\(?:begin\\|end\$\\|env_member_\$?:begin\\|end\$\\|s\$?:cenario_member_\\(?:begin\\|end\$\\|ubenv_member_\$?:begin\\|end\$\\)\\|xactor_member_\$?:begin\\|end\$\\)\\|while\\)\\|always\$?:_\\(?:comb\\|ff\\|latch\$\\)?\\|begin\\|c\$?:ase[xz]?\\|l\\(?:ass\\|ocking\$\\|o\$?:nfig\\|vergroup\$\\)\\|end\$?:c\\(?:ase\\|l\\(?:ass\\|ocking\$\\|onfig\\)\\|function\\|g\$?:enerate\\|roup\$\\|interface\\|module\\|p\$?:ackage\\|r\\(?:imitive\\|o\\(?:gram\\|perty\$\\)\\)\\|s\$?:equence\\|pecify\$\\|ta\$?:ble\\|sk\$\\)?\\|f\$?:inal\\|ork\\|unction\$\\|generate\\|in\$?:itial\\|terface\$\\|join\$?:_\\(?:any\\|none\$\\)?\\|m\$?:\\(?:acrom\$?odule\\)\\|p\$?:ackage\\|r\\(?:imitive\\|o\\(?:gram\\|perty\$\\)\\)\\|rand\$?:\\(?:cas\\|sequenc\$e\\)\\|s\$?:equence\\|pecify\$\\|ta\$?:ble\\|sk\$\\|virtual\\|{\\)\\>")
(defconst verilog-defun-level-not-generate-re "\\<\$c\\(?:lass\\|onfig\$\\|interface\\|m\$?:\\(?:acrom\$?odule\\)\\|p\$?:ackage\\|r\\(?:imitive\\|ogram\$\\)\\)\\>")
(defconst verilog-defun-level-re "\\<\$always\\(?:_\\(?:comb\\|ff\\|latch\$\\)?\\|c\$?:lass\\|onfig\$\\|end\$?:function\\|task\$\\|final\\|in\$?:itial\\|terface\$\\|m\$?:\\(?:acrom\$?odule\\)\\|p\$?:ackage\\|r\\(?:imitive\\|ogram\$\\)\\)\\>")
(defconst verilog-defun-level-generate-only-re "\\<\$always\\(?:_\\(?:comb\\|ff\\|latch\$\\)?\\|end\$?:function\\|task\$\\|\$?:fin\\|initi\$al\\)\\>")
(defconst verilog-cpp-level-re "\\<\$end\\(?:class\\|interface\\|module\\|p\\(?:ackage\\|r\\(?:imitive\\|ogram\$\\)\\)\\)\\>")
(defconst verilog-dpi-import-export-re "\$\\<\\(import\\|export\$\\>\\s-+\"DPI\$-C\$?\"\\s-+\$\\<\\(context\\|pure\$\\>\\s-+\\)?\$[A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\$?\\<\$function\\|task\$\\>\\)")
(defconst verilog-default-clocking-re "\\<default\\s-+clocking\\s-+[A-Za-z_][A-Za-z0-9_]*\\s-*;")
(defconst verilog-disable-fork-re "\$disable\\|wait\$\\s-+fork\\>")
(defconst verilog-extended-case-re "\$\\(unique0?\\s-+\\|priority\\s-+\$?case[xz]?\\|randcase\\)")
(defconst verilog-extended-complete-re (concat "\$\\(\\<extern\\s-+\\|\\<\\(\\<\\(pure\\|context\$\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\|\\<static\\s-+\\)*\$\\<function\\>\\|\\<task\\>\$\\)\\|\$\\(\\<typedef\\>\\s-+\$*\$\\<struct\\>\\|\\<union\\>\\|\\<class\\>\$\\)\\|\$\\(\\<\\(import\\|export\$\\>\\s-+\\)?\$\"DPI\\(-C\$?\"\\s-+\\)?\$\\<\\(pure\\|context\$\\>\\s-+\\)?\$[A-Za-z_][A-Za-z0-9_]*\\s-*=\\s-*\$?\$function\\>\\|task\\>\$\\)\\|" verilog-extended-case-re))
(defconst verilog-basic-complete-re "\\<\$a\\(?:lways\\(?:_\\(?:comb\\|ff\\|latch\$\\)?\\|ss\$?:ert\\|ign\$\\)\\|constraint\\|do\\|else\\|f\$?:inal\\|or\\(?:e\\(?:ach\\|ver\$\\)?\\)\\|i\$?:f\\|mport\\|nitial\$\\|localparam\\|m\$?:\\(?:acrom\$?odule\\)\\|parameter\\|r\$?:andcase\\|epeat\$\\|while\\)\\>")
(defconst verilog-complete-reg (concat verilog-extended-complete-re "\\|\$" verilog-basic-complete-re "\$"))
(defconst verilog-end-statement-re (concat "\$" verilog-beg-block-re "\$\\|\$" verilog-end-block-re "\$"))
(defconst verilog-endcase-re (concat verilog-extended-case-re "\\|\$endcase\$\\|" verilog-defun-re))
#@49 String used to mark beginning of excluded text.
(defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----" (#$ . 83396))
#@43 String used to mark end of excluded text.
(defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */" (#$ . 83542))
(defconst verilog-preprocessor-re "\$?:\\<\\(`\\(?:__\\(?:\\(?:FIL\\|LIN\$E__\\)\\|celldefine\\|e\$?:lse\\|nd\\(?:_keywords\\|celldefine\\|if\$\\)\\|nounconnected_drive\\|resetall\\|un\$?:connected_drive\\|defineall\$\\)\\)\\>\\)\\|\$?:\\<\\(`elsif\\|`ifn?def\\|`undef\\|`default_nettype\\|`begin_keywords\$\\>\\s-\\)\\|\$?:\\<\\(`line\$\\>\\s-+[0-9]+\\s-+\"[^\"]+\"\\s-+[012]\\)\\|\$?:\\<\\(`include\$\\>\\s-+\$?:\"[^\"]+\"\\|<[^>]+>\$\\)\\|\$?:\\<\\(`pragma\$\\>\\s-+.+$\\)\\|\$?:\\<\\(`timescale\$\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*/\\s-*10\\{0,2\\}\\s-*[munpf]?s\\)\\|\$?:\\<\\(`define\\|`if\$\\>\\s-+\$?:.*?\\(?:\n.*\$*?\\)\$?:\n\\s-*\n\\|\\'\$\\)\\|\$?:\\<`\\w+\\>\\s-*(\\(?:.*?\\(?:\n.*\$*?\\)\$?:\n\\s-*\n\\|\\'\$\\)")
#@27 List of Verilog keywords.
(defconst verilog-keywords (append verilog-compiler-directives '("after" "alias" "always" "always_comb" "always_ff" "always_latch" "and" "assert" "assign" "assume" "automatic" "before" "begin" "bind" "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte" "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos" "config" "const" "constraint" "context" "continue" "cover" "covergroup" "coverpoint" "cross" "deassign" "default" "defparam" "design" "disable" "dist" "do" "edge" "else" "end" "endcase" "endclass" "endclocking" "endconfig" "endfunction" "endgenerate" "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive" "endprogram" "endproperty" "endspecify" "endsequence" "endtable" "endtask" "enum" "event" "expect" "export" "extends" "extern" "final" "first_match" "for" "force" "foreach" "forever" "fork" "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if" "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir" "include" "initial" "inout" "input" "inside" "instance" "int" "integer" "interface" "intersect" "join" "join_any" "join_none" "large" "liblist" "library" "local" "localparam" "logic" "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module" "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not" "notif0" "notif1" "null" "or" "output" "package" "packed" "parameter" "pmos" "posedge" "primitive" "priority" "program" "property" "protected" "pull0" "pull1" "pulldown" "pullup" "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc" "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg" "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal" "showcancelled" "signed" "small" "solve" "specify" "specparam" "static" "string" "strong0" "strong1" "struct" "super" "supply0" "supply1" "table" "tagged" "task" "this" "throughout" "time" "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union" "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void" "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard" "wire" "with" "within" "wor" "xnor" "xor" "accept_on" "checker" "endchecker" "eventually" "global" "implies" "let" "nexttime" "reject_on" "restrict" "s_always" "s_eventually" "s_nexttime" "s_until" "s_until_with" "strong" "sync_accept_on" "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak" "implements" "interconnect" "nettype" "soft")) (#$ . 84439))
#@48 Dual comment value for `comment-start-regexp'.
(defconst verilog-comment-start-regexp "//\\|/\\*" (#$ . 86995))
#@44 Syntax table used in Verilog mode buffers.
(defvar verilog-mode-syntax-table (byte-code "\301 \302\303\304#\210\302\305\306#\210\302\307\306#\210\302\310\306#\210\302\311\306#\210\302\312\306#\210\302\313\306#\210\302\314\306#\210\302\315\306#\210\302\316\317#\210\302\320\317#\210\302\321\306#\210\302\322\323#\210\302\324\325#\210\302\326\327#\210)\207" [table make-syntax-table modify-syntax-entry 92 "\\" 43 "." 45 61 37 60 62 38 124 96 "w" 95 39 47 ". 124b" 42 ". 23" 10 "> b"] 4) (#$ . 87113))
#@40 Default highlighting for Verilog mode.
(defvar verilog-font-lock-keywords nil (#$ . 87636))
#@46 Subdued level highlighting for Verilog mode.
(defvar verilog-font-lock-keywords-1 nil (#$ . 87734))
#@87 Medium level highlighting for Verilog mode.
See also `verilog-font-lock-extra-types'.
(defvar verilog-font-lock-keywords-2 nil (#$ . 87840))
#@86 Gaudy level highlighting for Verilog mode.
See also `verilog-font-lock-extra-types'.
(defvar verilog-font-lock-keywords-3 nil (#$ . 87987))
#@41 Font to use for translated off regions.
(defvar verilog-font-lock-translate-off-face 'verilog-font-lock-translate-off-face (#$ . 88133))
(custom-declare-face 'verilog-font-lock-translate-off-face '((((class color) (background light)) (:background "gray90" :italic t)) (((class color) (background dark)) (:background "gray10" :italic t)) (((class grayscale) (background light)) (:foreground "DimGray" :italic t)) (((class grayscale) (background dark)) (:foreground "LightGray" :italic t)) (t (:italis t))) "Font lock mode face used to background highlight translate-off regions." :group 'font-lock-highlighting-faces)
#@42 Obsolete font to use for p1800 keywords.
(defvar verilog-font-lock-p1800-face 'verilog-font-lock-p1800-face (#$ . 88756))
(byte-code "\300\301\302\303\304\305%\210\306\301\307\310#\207" [custom-declare-face verilog-font-lock-p1800-face ((((class color) (background light)) (:foreground "DarkOrange3" :bold t)) (((class color) (background dark)) (:foreground "orange1" :bold t)) (t (:italic t))) "Font lock mode face used to highlight P1800 keywords." :group font-lock-highlighting-faces make-obsolete-variable nil "27.1"] 6)
#@47 Font to use for Analog/Mixed Signal keywords.
(defvar verilog-font-lock-ams-face 'verilog-font-lock-ams-face (#$ . 89287))
(custom-declare-face 'verilog-font-lock-ams-face '((((class color) (background light)) (:foreground "Purple" :bold t)) (((class color) (background dark)) (:foreground "orange1" :bold t)) (t (:italic t))) "Font lock mode face used to highlight AMS keywords." :group 'font-lock-highlighting-faces)
#@65 Font to use for Verilog Grouping Keywords (such as begin..end).
(defvar verilog-font-lock-grouping-keywords-face 'verilog-font-lock-grouping-keywords-face (#$ . 89712))
(byte-code "\306\307\310\311\312\313%\210\314\315\316\317\320\321\322Q\321\f\323Q
\203\"�\307\202#�\324B\321\323Q\324B\321\n\323Q\325BF'\326'\327\330\331E\332\333\334E\335\336F\"(\326(\337	\340Q\341\342\343\344\345\257\")\326)*\205_�\346C\"+-\306\207" [verilog-type-font-keywords verilog-pragma-keywords verilog-ams-keywords verilog-font-general-keywords verilog-font-grouping-keywords verilog-highlight-grouping-keywords custom-declare-face verilog-font-lock-grouping-keywords-face ((((class color) (background light)) (:foreground "Purple" :bold t)) (((class color) (background dark)) (:foreground "orange1" :bold t)) (t (:italic t))) "Font lock mode face used to highlight verilog grouping keywords." :group font-lock-highlighting-faces "\$?:and\\|b\\(?:it\\|uf\\(?:if[01]\$?\\|yte\\)\\|c\$?:handle\\|mos\\|onst\$\\|defparam\\|e\$?:num\\|vent\$\\|genvar\\|highz[01]\\|in\$?:out\\|put\\|t\\(?:e\\(?:ger\\|rconnect\$\\)?\\)\\|lo\$?:calparam\\|gic\\|ngint\$\\|mailbox\\|n\$?:and\\|ettype\\|mos\\|o\\(?:tif[01]\\|[rt]\$\\)\\|o\$?:r\\|utput\$\\|p\$?:a\\(?:cked\\|rameter\$\\|mos\\|ull\$?:down\\|up\\|[01]\$\\)\\|r\$?:cmos\\|e\\(?:al\\(?:time\$?\\|[fg]\\)\\|nmos\\|pmos\\|tran\$?:if[01]\$?\\)\\|s\$?:emaphore\\|hort\\(?:int\\|real\$\\|igned\\|pecparam\\|t\$?:atic\\|r\\(?:ing\\|ong[01]\\|uct\$\\)\\|upply[01]?\\)\\|t\$?:ime\\|r\\(?:an\\(?:if[01]\$?\\|i\$?:and\\|or\\|reg\\|[01]\$?\\)\\|ype\$?:def\$?\\)\\|u\$?:n\\(?:ion\\|signed\$\\|wire\\)\\|v\$?:ar\\|ectored\$\\|w\$?:and\\|eak[01]\\|ire\\|or\$\\|x\$?:n?or\$\\)" "\$?:0in\\|auto\\|leda\\|rtl_synthesis\\|s\\(?:urefire\\|ynopsys\$\\|verilint\\)" "\$?:a\\(?:b\\(?:ove\\|s\\(?:delay\\|tol\$?\\)\\|c\$?:_stim\\|cess\\|osh?\$\\|liasparam\\|nal\$?:og\\|ysis\$\\|sinh?\\|tan[2h]?\\)\\|branch\\|c\$?:eil\\|o\\(?:n\\(?:nect\\(?:module\\|rules\$?\\|tinuous\\)\\|sh?\\)\\)\\|d\$?:d\\(?:t_nature\\|[tx]\$\\|isc\$?:\\(?:iplin\\|ret\$e\\)\\|omain\\|river_update\\)\\|e\$?:nd\\(?:connectrules\\|discipline\\|nature\\|paramset\$\\|x\$?:clude\\|p\$\\)\\|f\$?:inal_step\\|l\\(?:icker_noise\\|o\\(?:or\\|w\$\\)\\|rom\\)\\|ground\\|hypot\\|i\$?:dt\\(?:_nature\\|mod\$?\\|n\$?:f\\|itial_step\$\\)\\|l\$?:a\\(?:place_\\(?:n[dp]\\|z[dp]\$\\|st_crossing\\)\\|imexp\\|n\\|og\\)\\|m\$?:ax\\|erged\\|in\$\\|n\$?:ature\\|et_resolution\\|oise_table\$\\|p\$?:aramset\\|o\\(?:tential\\|w\$\\)\\|resolveto\\|s\$?:inh?\\|lew\\|\\(?:pli\\|qr\$t\\)\\|t\$?:anh?\\|imer\\|ransition\$\\|units\\|w\$?:hite_noise\\|real\$\\|zi_\$?:n[dp]\\|z[dp]\$\\)" "\$?:a\\(?:ccept_on\\|l\\(?:ias\\|ways\\(?:_\\(?:comb\\|ff\\|latch\$\\)?\\)\\|ss\$?:ert\\|ign\\|ume\$\\|utomatic\\)\\|b\$?:efore\\|in\\(?:sof\\|[ds]\$\\|reak\\)\\|c\$?:ase[xz]?\\|ell\\|hecker\\|l\\(?:ass\\|ocking\$\\|o\$?:n\\(?:fig\\|straint\\|t\\(?:ext\\|inue\$\\)\\|ver\$?:group\\|point\$?\\)\\|ross\\)\\|d\$?:e\\(?:assign\\|fault\\|sign\$\\|is\$?:able\\|t\$\\|o\\)\\|e\$?:dge\\|lse\\|nd\\(?:c\\(?:ase\\|hecker\\|l\\(?:ass\\|ocking\$\\|onfig\\)\\|function\\|g\$?:enerate\\|roup\$\\|interface\\|module\\|p\$?:ackage\\|r\\(?:imitive\\|o\\(?:gram\\|perty\$\\)\\)\\|s\$?:equence\\|pecify\$\\|ta\$?:ble\\|sk\$\\)\\|ventually\\|x\$?:p\\(?:\\(?:ec\\|or\$t\\)\\|te\$?:nds\\|rn\$\\)\\)\\|f\$?:i\\(?:nal\\|rst_match\$\\|or\$?:ce\\|e\\(?:ach\\|ver\$\\|k\$?:join\$?\\)?\\|unction\\)\\|g\$?:enerate\\|lobal\$\\|i\$?:f\\(?:f\\|none\$?\\|gnore_bins\\|llegal_bins\\|mp\$?:l\\(?:\\(?:ement\\|ie\$s\\)\\|ort\\)\\|n\$?:c\\(?:dir\\|lude\$\\|itial\\|s\$?:\\(?:id\\|tanc\$e\\)\\|ter\$?:face\\|sect\$\\)\\)\\|join\$?:_\\(?:any\\|none\$\\)?\\|l\$?:arge\\|et\\|ib\\(?:list\\|rary\$\\|ocal\\)\\|m\$?:a\\(?:cromodule\\|tches\$\\|edium\\|od\$?:port\\|ule\$\\)\\|n\$?:e\\(?:gedge\\|w\\|xttime\$\\|oshowcancelled\\|ull\\)\\|p\$?:ackage\\|osedge\\|r\\(?:i\\(?:mitive\\|ority\$\\|o\$?:gram\\|perty\\|tected\$\\)\\|u\$?:lsestyle_on\\(?:\\(?:detec\\|even\$t\\)\\|re\\)\\)\\|r\$?:and\\(?:c\\(?:ase\$?\\|sequence\\)?\\|e\$?:ject_on\\|lease\\|peat\\|strict\\|turn\$\\)\\|s\$?:_\\(?:always\\|eventually\\|nexttime\\|until\\(?:_with\$?\\)\\|calared\\|equence\\|howcancelled\\|mall\\|o\$?:ft\\|lve\$\\|pecify\\|tr\$?:ength\\|ong\$\\|uper\\|ync_\$?:\\(?:accep\\|rejec\$t_on\\)\\)\\|t\$?:a\\(?:ble\\|gged\\|sk\$\\|h\$?:is\\|roughout\$\\|ime\$?:precision\\|unit\$\\)\\|u\$?:n\\(?:ique0?\\|t\\(?:il\\(?:_with\$?\\|yped\\)\\)\\|se\\)\\|v\$?:irtual\\|oid\$\\|w\$?:ait\\(?:_order\$?\\|eak\\|hile\\|i\$?:ldcard\\|th\\(?:in\$?\\)\\)\\)" "\$?:begin\\|end\$" "\\<\$" "\\|\\$[a-zA-Z][a-zA-Z0-9_\\$]*\$\\>" "\\)\\>" font-lock-type-face verilog-font-lock-ams-face append "\\<\$\\(macro\$?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\$\\sw+\$" (1 font-lock-keyword-face) (3 font-lock-function-name-face 'prepend) "\\<function\\>\\s-+\$integer\\|real\\(time\$?\\|time\\)\\s-+\$\\sw+\$" (1 font-lock-keyword-face) (3 font-lock-constant-face prepend) ("\\<function\\>\\s-+\$\\[[^]]+\\]\$\\s-+\$\\sw+\$" (1 font-lock-keyword-face) (2 font-lock-constant-face append)) ("\\<function\\>\\s-+\$\\sw+\$" 1 'font-lock-constant-face append) "\$//\\s-*\\(" "\$\\s-.*\\)" ("\$\\\\\\S-*\\s-\$" 0 font-lock-function-name-face) ("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face) 'font-lock-preprocessor-face 'font-lock-type-face)) ("\$@\$\\|\$[ 	\n\f
]#\\s-*\\(\\([0-9_.]+\\('s?[hdxbo][0-9a-fA-F_xz]*\$?\\)\\|\$([^()]+)\\|\\sw+\$\\)\\)" 0 font-lock-type-face append) ("\$##\\(\\sw+\\|\\[[^]]+\\]\$\\)" 0 font-lock-type-face append) ("\$[A-Za-z][A-Za-z0-9_]*\$\\s-*(" 1 font-lock-function-name-face) (verilog-match-translate-off (0 'verilog-font-lock-translate-off-face prepend)) verilog-font-lock-keywords verilog-font-lock-keywords-1 verilog-font-lock-keywords-2 verilog-highlight-translate-off verilog-font-lock-keywords-3] 8)
#@433 Execute BODY forms, saving state around insignificant change.
Changes in text properties like `face' or `syntax-table' are
considered insignificant.  This macro allows text properties to
be changed, even in a read-only buffer.

A change is considered significant if it affects the buffer text
in any way that isn't completely restored again.  Any
user-visible changes to the buffer must not be within a
`verilog-save-buffer-state'.
(defalias 'verilog-save-buffer-state '(macro . #[(&rest body) "\301\302\303\304!\203�\304B\202�\305\306\307\310B\311BBEE\207" [body let ((inhibit-point-motion-hooks t) (verilog-no-change-functions t)) fboundp with-silent-modifications let* ((modified (buffer-modified-p)) (buffer-undo-list t) (inhibit-read-only t) (inhibit-modification-hooks t) before-change-functions after-change-functions deactivate-mark buffer-file-name buffer-file-truename) unwind-protect progn ((and (not modified) (buffer-modified-p) (verilog-restore-buffer-modified-p nil)))] 7 (#$ . 95782)]))
#@77 Local variable when inside a `verilog-save-font-no-change-functions' block.
(defvar verilog-save-font-mod-hooked nil (#$ . 96795))
(make-variable-buffer-local 'verilog-save-font-mod-hooked)
#@332 Execute BODY forms, disabling all change hooks in BODY.
Includes temporary disabling of `font-lock' to restore the buffer
to full text form for parsing.  Additional actions may be specified with
`verilog-before-save-font-hook' and `verilog-after-save-font-hook'.
For insignificant changes, see instead `verilog-save-buffer-state'.
(defalias 'verilog-save-font-no-change-functions '(macro . #[(&rest body) "\301\302\303B\304\305\306\307\310\305\311\303BE\312BBF\257\207" [body if verilog-save-font-mod-hooked progn (verilog-run-hooks 'verilog-before-save-font-hook) let* ((verilog-save-font-mod-hooked (- (point-max) (point-min))) (fontlocked (when (and (boundp 'font-lock-mode) font-lock-mode) (font-lock-mode 0) t))) (run-hook-with-args 'before-change-functions (point-min) (point-max)) unwind-protect ((inhibit-point-motion-hooks t) (inhibit-modification-hooks t) (verilog-no-change-functions t) before-change-functions after-change-functions) ((run-hook-with-args 'after-change-functions (point-min) (point-max) verilog-save-font-mod-hooked) (when fontlocked (font-lock-mode t)) (verilog-run-hooks 'verilog-after-save-font-hook))] 12 (#$ . 96992)]))
#@158 If true, the specified buffer's comment properties are static.
Buffer changes will be ignored.  See `verilog-inside-comment-or-string-p'
and `verilog-scan'.
(defvar verilog-scan-cache-preserving nil (#$ . 98155))
#@63 Modification tick at which `verilog-scan' was last completed.
(defvar verilog-scan-cache-tick nil (#$ . 98374))
(make-variable-buffer-local 'verilog-scan-cache-tick)
#@33 Flush the `verilog-scan' cache.
(defalias 'verilog-scan-cache-flush #[nil "\301\211\207" [verilog-scan-cache-tick nil] 2 (#$ . 98546)])
#@43 Return t if the scan cache is up to date.
(defalias 'verilog-scan-cache-ok-p #[nil "\203�p=\203�	\206�	\302 \232\207" [verilog-scan-cache-preserving verilog-scan-cache-tick buffer-chars-modified-tick] 2 (#$ . 98689)])
#@128 Execute the BODY forms, allowing scan cache preservation within BODY.
This requires that insertions must use `verilog-insert'.
(defalias 'verilog-save-scan-cache '(macro . #[(&rest body) "\301\302\303\304\301BEE\207" [body progn (unless (verilog-scan-cache-ok-p) (setq verilog-scan-cache-tick nil)) let* ((verilog-scan-cache-preserving (current-buffer)))] 6 (#$ . 98919)]))
#@129 Parse between BEG and END for `verilog-inside-comment-or-string-p'.
This creates v-cmts properties where comments are in force.
(defalias 'verilog-scan-region #[(beg end) "\212\306 \307\216\310\211\311 \310\211\310\312\216\313b\210`W\205\243�\314\315!\203F�`\316\317\310#\204:�b\210\320T`\321\310$\210\202�\314\322!\203h�`\316\323\310#\204\\�b\210\320T`\321\310$\210\202�\314\324!\203\212�`\325\326\310#\204~�b\210\320T`\321\310$\210\202�\327u\210\325\330\310#\203\234�\331u\210\202�b\210\202�.\207" [save-match-data-internal verilog-no-change-functions inhibit-point-motion-hooks #1=#:modified buffer-undo-list inhibit-read-only match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] t buffer-modified-p #[nil "?\205�\301\302!\207" [#1# restore-buffer-modified-p nil] 2] nil looking-at "//" search-forward "\n" put-text-property v-cmts "/\\*" "*/" "\"" re-search-forward "[^\\]\"" 1 "[/\"]" -1 inhibit-modification-hooks pt beg end] 6 (#$ . 99301)])
#@190 Parse the buffer, marking all comments with properties.
Also assumes any text inserted since `verilog-scan-cache-tick'
either is ok to parse as a non-comment, or `verilog-insert' was used.
(defalias 'verilog-scan #[nil "\306 ?\205?�\212\307\211\310 \307\211\307\311\216\203&�\312\313p\314 %\210\315ed\316#\210\317ed\"\210\314 \205=�\312\320!.\207" [verilog-no-change-functions inhibit-point-motion-hooks #1=#:modified buffer-undo-list inhibit-read-only inhibit-modification-hooks verilog-scan-cache-ok-p t buffer-modified-p #[nil "?\205�\301\302!\207" [#1# restore-buffer-modified-p nil] 2] message "Scanning %s cache=%s cachetick=%S tick=%S" buffer-chars-modified-tick remove-text-properties (v-cmts nil) verilog-scan-region "Scanning... done" verilog-debug verilog-scan-cache-preserving verilog-scan-cache-tick] 7 (#$ . 100344)])
#@66 For debugging, show with display face results of `verilog-scan'.
(defalias 'verilog-scan-debug #[nil "\300\301!\210\212eb\210\302ed\303#\210m?\2054�\304`\305\"\203(�\306``T\307\310$\210\311u\210\202�\312`!\206/�db\210\202�)\207" [font-lock-mode 0 remove-text-properties (face nil) get-text-property v-cmts put-text-property face underline 1 next-property-change] 5 (#$ . 101201)])
#@61 For debugging, run `verilog-scan' and `verilog-scan-debug'.
(defalias 'verilog-scan-and-debug #[nil "\302\211eb\210\303 \210\304 *\207" [verilog-scan-cache-tick verilog-scan-cache-preserving nil verilog-scan verilog-scan-debug] 2 (#$ . 101590)])
#@163 Check if optional point POS is inside a comment.
This may require a slow pre-parse of the buffer with `verilog-scan'
to establish comment properties on all text.
(defalias 'verilog-inside-comment-or-string-p #[(&optional pos) "\301 \210\203�eY\205�\302\303\"\207\302`\303\"\207" [pos verilog-scan get-text-property v-cmts] 3 (#$ . 101845)])
#@190 Insert STUFF arguments, tracking for `verilog-inside-comment-or-string-p'.
Any insert that includes a comment must have the entire comment
inserted using a single call to `verilog-insert'.
(defalias 'verilog-insert #[(&rest stuff) "`	\203�	@c\210	A\211\204�\302`\")\207" [pt stuff verilog-scan-region] 4 (#$ . 102198)])
(defalias 'verilog-declaration-end #[nil "\300\301!\207" [search-forward ";"] 2])
#@147 Return text describing where POINTNUM or current point is (for errors).
Use filename, if current buffer being edited shorten to just buffer name.
(defalias 'verilog-point-text #[(&optional pointnum) "\302 p\232\203\f�\303 \206�\206�\303 \304\305\306e	\206�`\"T!Q\207" [buffer-file-name pointnum window-buffer buffer-name ":" int-to-string count-lines] 6 (#$ . 102612)])
#@45 Move backward over one balanced expression.
(defalias 'electric-verilog-backward-sexp #[nil "\300 \207" [verilog-backward-sexp] 1 (#$ . 102992) nil])
#@44 Move forward over one balanced expression.
(defalias 'electric-verilog-forward-sexp #[nil "\300 \207" [verilog-forward-sexp] 1 (#$ . 103148) nil])
#@25 Move forward ARG sexps.
(defalias 'verilog-forward-sexp-function #[(arg) "\301W\203	�\302 \207\303 \207" [arg 0 verilog-backward-sexp verilog-forward-sexp] 2 (#$ . 103301)])
(defalias 'verilog-backward-sexp #[nil "\306\307\306`\310\311!\204�\312\313!\210\314 \206M\310\315!\203\220�\f\316P	?\205M\306\317%&\320'\321&%
#\203[�\322 \211'\203[�\314 \203[�\323'%\203W�`%V\202X�\324\2041�\325'!\210\326\225,\205M\307\225\203q�\327 \210\202!�\330\225\203|�\nT\202!�\331\225\203!�\nS\211\326U\203!�\324\211\202\"�\310\f!\203\233�\327 \202M\310\332!\203H\307\225\203\346�\333\306\317%&\320'\321&%
#\203\333�\322 \211'\203\333�\314 \203\333�\323'%\203\327�`%V\202\330�\324\204\261�\325'!\210\326\225,\202M\330\225\203+\334\306\317%&\320'\321&%
#\203 \322 \211'\203 \314 \203 \323'%\203`%V\202\324\204\366�\325'!\210\326\225,\202M\331\225\203p\335\306\317%&\320'\321&%
#\203e\322 \211'\203e\314 \203e\323'%\203a`%V\202b\324\204;\325'!\210\326\225,\202M\336\225\203\265\337\306\317%&\320'\321&%
#\203\252\322 \211'\203\252\314 \203\252\323'%\203\246`%V\202\247\324\204\200\325'!\210\326\225,\202M\340\225\203\372\341\306\317%&\320'\321&%
#\203\357\322 \211'\203\357\314 \203\357\323'%\203\353`%V\202\354\324\204\305\325'!\210\326\225,\202M\342\225\203?\343\306\317%&\320'\321&%
#\2034\322 \211'\2034\314 \2034\323'%\2030`%V\2021\324\204\n\325'!\210\326\225,\202Mb\210\344\307!\202Mb\210\344 ,\207" [st found elsec reg verilog-end-block-re NOERROR nil 1 looking-at "\\<" forward-word-strictly -1 verilog-skip-backward-comment-or-string "\\<else\\>" "\\|\$\\<else\\>\$\\|\$\\<if\\>\$" move (nil nil) re-search-backward match-data (nil nil) t store-match-data 0 verilog-leap-to-head 2 3 "\$endmodule\\>\$\\|\$\\<endprimitive\\>\$\\|\$\\<endclass\\>\$\\|\$\\<endprogram\\>\$\\|\$\\<endinterface\\>\$\\|\$\\<endpackage\\>\$" "\\<\$macro\$?module\\>" "\\<primitive\\>" "\\<class\\>" 4 "\\<program\\>" 5 "\\<interface\\>" 6 "\\<package\\>" backward-sexp BOUND REGEXP mdata] 5])
(defalias 'verilog-forward-sexp #[nil "\306\307`\310\311\312!\204�\313\314!\210\315 \203�\316 \202\274\311\f!\203\347\317\225\203,�\320\202\360�\307\225\2038�\321\322\202\360�\323\225\203o�\306\311@!\204Y�\311\324!\203f�`\313\314!\210\311@!\203f�\325\225b\210\313\317!\210\306\202k�
b\210\326)\202\360�\327\225\203y�\330\202\360�\331\225\203\205�\332\333\202\360�\334\225\203\217�\335\202\360�\336\225\203\233�\337\333\202\360�\340\225\203\247�\337\333\202\360�\341\225\203\263�\342\333\202\360�\343\225\203\277�\342\333\202\360�\343\225\203\311�\344\202\360�\345\225\203\323�\346\202\360�\347\225\203\335�\350\202\360�\351\225\203\351�\352\322\202\360�\353\225\203\360�\354\205\274\313\317!\205\274\3552\274\310=\203\235\317\306A\306\356BCD\357E\360DCB#\203@\361 \211E\203@\315 \203@\362EC\203<`CW\202=\363\204\364E!\210\325\225,\205\231\n\225\203cAS\211A\325U\203	\365\355\317\"\210\202	\317\225\203	`\317\224b\210\311@!\204\206\311\324!\203\214\313\314!\210\311@!\203\214\325\225b\202\225
b\210AT\211A\210\202	*\202\343\306\356BCD\357E\360DCB#\203\324\361 \211E\203\324\315 \203\324\362EC\203\320`CW\202\321\363\204\251\364E!\210\325\225,\205\343\365\355\317\"0\202\274\311\366!\203\253\317\225\2034\367\306\356BCD\357E\360DCB#\203)\361 \211E\203)\315 \203)\362EC\203%`CW\202&\363\204\376\364E!\210\325\225,\202\274\307\225\203{\370\306\356BCD\357E\360DCB#\203p\361 \211E\203p\315 \203p\362EC\203l`CW\202m\363\204E\364E!\210\325\225,\202\274\322\225\203\302\371\306\356BCD\357E\360DCB#\203\267\361 \211E\203\267\315 \203\267\362EC\203\263`CW\202\264\363\204\214\364E!\210\325\225,\202\274\323\225\203	\372\306\356BCD\357E\360DCB#\203\376\361 \211E\203\376\315 \203\376\362EC\203\372`CW\202\373\363\204\323\364E!\210\325\225,\202\274\373\225\203P\374\306\356BCD\357E\360DCB#\203E\361 \211E\203E\315 \203E\362EC\203A`CW\202B\363\204\364E!\210\325\225,\202\274\327\225\203\227\375\306\356BCD\357E\360DCB#\203\214\361 \211E\203\214\315 \203\214\362EC\203\210`CW\202\211\363\204a\364E!\210\325\225,\202\274	b\210g\376U\203\245\317u\202\274\377\317!\202\274	b\210g\376U\203\271\317u\202\274\377\317!,\207" [nest st md reg verilog-beg-block-re-ordered here nil 2 yes looking-at "\\<" forward-word-strictly -1 verilog-skip-forward-comment-or-string verilog-forward-syntactic-ws 1 "\$\\<begin\\>\$\\|\$\\<end\\>\$" "\$\\<randcase\\>\\|\\(\\<unique0?\\>\\s-+\\|\\<priority\\>\\s-+\$?\\<case[xz]?\\>[^:]\\)\\|\$\\<endcase\\>\$" 3 4 "fork" 0 "\$\\<fork\\>\$\\|\$\\<join\\(_any\\|_none\$?\\>\\)" 6 "\$\\<class\\>\$\\|\$\\<endclass\\>\$" 7 "\\<endtable\\>" no 8 "\$\\<specify\\>\$\\|\$\\<endspecify\\>\$" 9 "\\<endfunction\\>" 10 11 "\\<endtask\\>" 12 "\$\\<generate\\>\$\\|\$\\<endgenerate\\>\$" 13 "\$\\<covergroup\\>\$\\|\$\\<endgroup\\>\$" 14 "\$\\<property\\>\$\\|\$\\<endproperty\\>\$" 15 "\$\\<\\(rand\$?sequence\\>\\)\\|\$\\<endsequence\\>\$" 17 "\$\\<clocking\\>\$\\|\$\\<endclocking\\>\$" skip move (nil nil) re-search-forward match-data (nil nil) t store-match-data throw "\$\\<\\(macro\$?module\\>\\)\\|\$\\<primitive\\>\$\\|\$\\<class\\>\$\\|\$\\<program\\>\$\\|\$\\<interface\\>\$\\|\$\\<package\\>\$" "\\<endmodule\\>" "\\<endprimitive\\>" "\\<endclass\\>" "\\<endprogram\\>" 5 "\\<endinterface\\>" "\\<endpackage\\>" 41 forward-sexp verilog-disable-fork-re depth NOERROR BOUND REGEXP mdata] 5])
(defalias 'verilog-declaration-beg #[nil "o\305\306\307\n	#\203,�\310 \211\203,�\311 \203,�\312\n\203(�`\nV\202)�\305\204�\313\f!\210\314\225,\207" [verilog-declaration-re NOERROR BOUND REGEXP mdata t (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) store-match-data 0] 4])
(defvar verilog-which-tool 1)
(defvar verilog-mode-hook nil)
(byte-code "\300\301N\204\f�\302\300\301\303#\210\304\305!\204�\302\305\306\307#\210\300\207" [verilog-mode-hook variable-documentation put "Hook run after entering Verilog mode.\nNo problems result if this variable is not bound.\n`add-hook' automatically binds it.  (This is true for all hook variables.)" boundp verilog-mode-map definition-name verilog-mode] 4)
(defvar verilog-mode-map (make-sparse-keymap))
(byte-code "\300\301N\204�\302\300\301\303\304!#\210\305\306!\204�\302\306\307\310#\210\311\312 !\210\306\301N\204-�\302\306\301\303\313!#\210\302\310\314\315#\207" [verilog-mode-map variable-documentation put purecopy "Keymap for `verilog-mode'." boundp verilog-mode-syntax-table definition-name verilog-mode (lambda (#1=#:def-tmp-var) (defvar verilog-mode-syntax-table #1#)) make-syntax-table "Syntax table for `verilog-mode'." derived-mode-parent prog-mode] 5)
#@6506 Major mode for editing Verilog code.
\<verilog-mode-map>
See \[describe-function] verilog-auto (\[verilog-auto]) for details on how
AUTOs can improve coding efficiency.

Use \[verilog-faq] for a pointer to frequently asked questions.

NEWLINE, TAB indents for Verilog code.
Delete converts tabs to spaces as it moves back.

Supports highlighting.

Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
with no args, if that value is non-nil.

Variables controlling indentation/edit style:

variable `verilog-indent-level'      (default 3)
   Indentation of Verilog statements with respect to containing block.
 `verilog-indent-level-module'        (default 3)
   Absolute indentation of Module level Verilog statements.
   Set to 0 to get initial and always statements lined up
   on the left side of your screen.
 `verilog-indent-level-declaration'   (default 3)
   Indentation of declarations with respect to containing block.
   Set to 0 to get them list right under containing block.
 `verilog-indent-level-behavioral'    (default 3)
   Indentation of first begin in a task or function block
   Set to 0 to get such code to lined up underneath the task or
   function keyword.
 `verilog-indent-level-directive'     (default 1)
   Indentation of \=`ifdef/\=`endif blocks.
 `verilog-cexp-indent'              (default 1)
   Indentation of Verilog statements broken across lines i.e.:
      if (a)
        begin
 `verilog-case-indent'              (default 2)
   Indentation for case statements.
 `verilog-auto-newline'             (default nil)
   Non-nil means automatically newline after semicolons and the punctuation
   mark after an end.
 `verilog-auto-indent-on-newline'   (default t)
   Non-nil means automatically indent line after newline.
 `verilog-tab-always-indent'        (default t)
   Non-nil means TAB in Verilog mode should always reindent the current line,
   regardless of where in the line point is when the TAB command is used.
 `verilog-indent-begin-after-if'    (default t)
   Non-nil means to indent begin statements following a preceding
   if, else, while, for and repeat statements, if any.  Otherwise,
   the begin is lined up with the preceding token.  If t, you get:
      if (a)
         begin // amount of indent based on `verilog-cexp-indent'
   otherwise you get:
      if (a)
      begin
 `verilog-auto-endcomments'         (default t)
   Non-nil means a comment /* ... */ is set after the ends which ends
   cases, tasks, functions and modules.
   The type and name of the object will be set between the braces.
 `verilog-minimum-comment-distance' (default 10)
   Minimum distance (in lines) between begin and end required before a comment
   will be inserted.  Setting this variable to zero results in every
   end acquiring a comment; the default avoids too many redundant
   comments in tight quarters.
 `verilog-auto-lineup'              (default `declarations')
   List of contexts where auto lineup of code should be done.

Variables controlling other actions:

`verilog-linter'                   (default `none')
   Unix program to call to run the lint checker.  This is the default
   command for \[compile-command] and \[verilog-auto-save-compile].

See \[customize] for the complete list of variables.

AUTO expansion functions are, in part:

\[verilog-auto]  Expand AUTO statements.
    \[verilog-delete-auto]  Remove the AUTOs.
    \[verilog-inject-auto]  Insert AUTOs for the first time.

Some other functions are:

\[completion-at-point]    Complete word with appropriate possibilities.
    \[verilog-mark-defun]  Mark function.
    \[verilog-beg-of-defun]  Move to beginning of current function.
    \[verilog-end-of-defun]  Move to end of current function.
    \[verilog-label-be]  Label matching begin ... end, fork ... join, etc statements.

\[verilog-comment-region]  Put marked area in a comment.
    \[verilog-uncomment-region]  Uncomment an area commented with \[verilog-comment-region].
    \[verilog-insert-block]  Insert begin ... end.
    \[verilog-star-comment]    Insert /* ... */.

\[verilog-sk-always]  Insert an always @(AS) begin .. end block.
    \[verilog-sk-begin]  Insert a begin .. end block.
    \[verilog-sk-case]  Insert a case block, prompting for details.
    \[verilog-sk-for]  Insert a for (...) begin .. end block, prompting for details.
    \[verilog-sk-generate]  Insert a generate .. endgenerate block.
    \[verilog-sk-header]  Insert a header block at the top of file.
    \[verilog-sk-initial]  Insert an initial begin .. end block.
    \[verilog-sk-fork]  Insert a fork begin .. end .. join block.
    \[verilog-sk-module]  Insert a module .. (/*AUTOARG*/);.. endmodule block.
    \[verilog-sk-ovm-class]  Insert an OVM Class block.
    \[verilog-sk-uvm-object]  Insert an UVM Object block.
    \[verilog-sk-uvm-component]  Insert an UVM Component block.
    \[verilog-sk-primitive]  Insert a primitive .. (.. );.. endprimitive block.
    \[verilog-sk-repeat]  Insert a repeat (..) begin .. end block.
    \[verilog-sk-specify]  Insert a specify .. endspecify block.
    \[verilog-sk-task]  Insert a task .. begin .. end endtask block.
    \[verilog-sk-while]  Insert a while (...) begin .. end block, prompting for details.
    \[verilog-sk-casex]  Insert a casex (...) item: begin.. end endcase block, prompting for details.
    \[verilog-sk-casez]  Insert a casez (...) item: begin.. end endcase block, prompting for details.
    \[verilog-sk-if]  Insert an if (..) begin .. end block.
    \[verilog-sk-else-if]  Insert an else if (..) begin .. end block.
    \[verilog-sk-comment]  Insert a comment block.
    \[verilog-sk-assign]  Insert an assign .. = ..; statement.
    \[verilog-sk-function]  Insert a function .. begin .. end endfunction block.
    \[verilog-sk-input]  Insert an input declaration, prompting for details.
    \[verilog-sk-output]  Insert an output declaration, prompting for details.
    \[verilog-sk-state-machine]  Insert a state machine definition, prompting for details.
    \[verilog-sk-inout]  Insert an inout declaration, prompting for details.
    \[verilog-sk-wire]  Insert a wire declaration, prompting for details.
    \[verilog-sk-reg]  Insert a register declaration, prompting for details.
    \[verilog-sk-define-signal]  Define signal under point as a register at the top of the module.

All key bindings can be seen in a Verilog-buffer with \[describe-bindings].
Key bindings specific to `verilog-mode-map' are:

\{verilog-mode-map}
(defalias 'verilog-mode #[nil "\306\300!\210\307\310 \210\311\312\310\313N\203�\314\311\313\310\313N#\210\315!\204'�\316\317 \"\210\320\f!\211\2036�
\321 =\203<�\322\f\323 \"\210)\324!\210\325\f!\210@A\306\326!\210\327\306\330!\210\331\325\f!\210\306\332!\210\333\306\334!\210\335\306\336!\210\337\306\340!\210\341 \306\342!\210\343\"\306\344!\210\345$\306\346!\210\337&\347B\350C\351 \210\352\353!\203\241�\354\353\355\307#\210\306\356!\210\357\337\211\211\360\361!?\205\261�\327\257.D\204\317�\354\362\363\307\211$\210\354\364\363\307\211$\210\354\365\366\307\211$\210\306\367!\210E7\352\370!\203\366�8<\203\366�\3118>\203\360�8\210\202\366�\3118B8\352\371!\203	\3119\236\204	\3729B9\354\373\374\337\375$\210\354\352\376!\203\376\202\377\201F�\337\375$\210)\201G�\201H�!\207" [delay-mode-hooks major-mode mode-name verilog-mode-map verilog-mode-syntax-table parent make-local-variable t prog-mode verilog-mode "Verilog" mode-class put keymap-parent set-keymap-parent current-local-map char-table-parent standard-syntax-table set-char-table-parent syntax-table use-local-map set-syntax-table beginning-of-defun-function verilog-beg-of-defun end-of-defun-function verilog-end-of-defun indent-line-function verilog-indent-line-relative comment-indent-function verilog-comment-indent parse-sexp-ignore-comments nil comment-start "// " comment-end "" comment-start-skip "/\\*+ *\\|// *" comment-multi-line 1 verilog-linter verilog-set-compile-command boundp hack-local-variables-hook add-hook verilog-modify-compile-command font-lock-defaults (verilog-font-lock-keywords verilog-font-lock-keywords-1 verilog-font-lock-keywords-2 verilog-font-lock-keywords-3) functionp syntax-ppss font-lock-mode-hook verilog-highlight-buffer font-lock-after-fontify-buffer-hook after-change-functions verilog-highlight-region imenu-generic-expression which-func-modes hs-special-modes-alist (verilog-mode "\\<begin\\>" "\\<end\\>" nil verilog-forward-sexp-function) completion-at-point-functions verilog-completion-at-point local write-contents-hooks write-contents-functions verilog-mode-abbrev-table local-abbrev-table verilog-which-tool verilog-tool noninteractive verilog-imenu-generic-expression verilog-auto-save-check run-mode-hooks verilog-mode-hook] 7 (#$ . 110269) nil])
#@51 Initialize speedbar to understand `verilog-mode'.
(defalias 'verilog-speedbar-initialize #[nil "\211\205�	@A\302=\203�\303	@@!\210	A\211\204�\304)\207" [auto-mode-alist mode-alist verilog-mode speedbar-add-supported-extension nil] 3 (#$ . 119087)])
(eval-after-load "speedbar" #[nil "\300 \207" [verilog-speedbar-initialize] 1])
#@95 Terminate line and indent next line.
With optional ARG, remove existing end of line comments.
(defalias 'electric-verilog-terminate-line #[(&optional arg) "\212\306 )\3078\203&�l\203�\310 \210\311 \210\202!�\311 \210\312c\210\313 \210\314 \202\227�\3158\2034�\311 \210\316 \202\227�l\203\225�\212\310 \210\313 \210\317\320w\210\321	!\203g�\314 \203U�\322\n\f\"\210\320\210\310 \210\f\204b�\311 \210)\320\202n�\320\210\310 \210\323)\203\210�
\324=\204~�
\325=\203\202�\326\327!\210\311 \210\202\213�\330y\210\205\227�\314 \202\227�\311 )\207" [state verilog-auto-end-comment-lines-re indent-str verilog-auto-endcomments arg verilog-auto-lineup verilog-syntax-ppss 7 delete-horizontal-space newline "// " beginning-of-line verilog-indent-line 4 verilog-more-comment " 	" nil looking-at verilog-set-auto-endcomments t all assignments verilog-pretty-expr :quiet 1 verilog-auto-indent-on-newline] 3 (#$ . 119428) nil])
#@53 Insert a newline and indent for the next statement.
(defalias 'electric-verilog-terminate-and-indent #[nil "\300\301!\207" [electric-verilog-terminate-line 1] 2 (#$ . 120358) nil])
#@45 Insert `;' character and reindent the line.
(defalias 'electric-verilog-semi #[nil "\301 \210\302 \206\n�\303 ?\205%�\212\304 \210\305 \210\306 \210)\205%�\307 ?\205%�\310 \207" [verilog-auto-newline verilog-insert-last-command-event verilog-in-comment-or-string-p verilog-in-escaped-name-p beginning-of-line verilog-forward-ws&directives verilog-indent-line verilog-parenthesis-depth electric-verilog-terminate-line] 1 (#$ . 120545) nil])
#@65 Insert `;' character, reindent the line and indent for comment.
(defalias 'electric-verilog-semi-with-comment #[nil "\300c\210\212\301 \210\302 \210)\303 \207" [";" beginning-of-line verilog-indent-line indent-for-comment] 1 (#$ . 120992) nil])
#@69 Insert `:' and do all indentations except line indent on this line.
(defalias 'electric-verilog-colon #[nil "\302 \210\303\304\305 `\"8\206�\306 ??\205&�\212`\307 \210`\211b\210\310!\210\311 +\207" [lim p verilog-insert-last-command-event 3 parse-partial-sexp line-beginning-position verilog-in-case-region-p verilog-beg-of-statement verilog-backward-case-item verilog-indent-line] 5 (#$ . 121243) nil])
#@70 Insert back-tick, and indent to column 0 if this is a CPP directive.
(defalias 'electric-verilog-tick #[nil "\300 \210\212\301 \205�\302 )\207" [verilog-insert-last-command-event verilog-in-directive-p verilog-indent-line] 1 (#$ . 121657) nil])
#@54 Function called when TAB is pressed in Verilog mode.
(defalias 'electric-verilog-tab #[nil "\305 \203�\306 \307 =\204�\310\306 \307 \311#\207\204#�\212\312\311x\210n)\203s�`\212\313 \210\312\311w\210\314 \210\315 \210`)`\nW\203A�\315 \202q�?\206q�l\204O�\311\202q�\316 \210l\205q�	`U\205q�\313 \210\317\f	\320#\210\321\224b\210\312\311x\210\322`	\"*\207\323c\207" [verilog-tab-always-indent oldpnt boi-point verilog-tab-to-comment comment-start-skip region-active-p region-beginning region-end indent-region nil " 	" beginning-of-line verilog-indent-line back-to-indentation indent-for-comment re-search-forward move 0 kill-region "	"] 4 (#$ . 121909) nil])
#@115 Indent-region the entire buffer as Verilog code.
To call this from the command line, see \[verilog-batch-indent].
(defalias 'verilog-indent-buffer #[nil "\300 \210\301 \210\302ed\303#\207" [verilog-mode verilog-auto-reeval-locals indent-region nil] 4 (#$ . 122581) nil])
#@73 Insert Verilog begin ... end; block in the code with right indentation.
(defalias 'verilog-insert-block #[nil "\300 \210\301c\210\302 \210\212\302 \210\303c\210\304 \210\300 )\207" [verilog-indent-line "begin" electric-verilog-terminate-line "end" beginning-of-line] 1 (#$ . 122858) nil])
#@39 Insert Verilog star comment at point.
(defalias 'verilog-star-comment #[nil "\300 \210\301c\210\212\302 \210\303c\210)\302 \210\304c\207" [verilog-indent-line "/*" newline " */" " * "] 1 (#$ . 123153) nil])
#@159 Use format string FMT to insert integers 0 to MAX - 1.
Inserts one integer per line, at the current column.  Stops early
if it reaches the end of the buffer.
(defalias 'verilog-insert-1 #[(fmt max) "i\304\212\nW\205(�\305\"c\210\306y\210m\203�\n\211\202�T\307	!\210\202�+\207" [n col max fmt 0 format 1 move-to-column] 4 (#$ . 123367)])
#@755 Insert a set of indices into a rectangle.
The upper left corner is defined by point.  Indices begin with 0
and extend to the MAX - 1.  If no prefix arg is given, the user
is prompted for a value.  The indices are surrounded by square
brackets [].  For example, the following code with the point
located after the first `a' gives:

a = b                           a[  0] = b
    a = b                           a[  1] = b
    a = b                           a[  2] = b
    a = b                           a[  3] = b
    a = b   ==> insert-indices ==>  a[  4] = b
    a = b                           a[  5] = b
    a = b                           a[  6] = b
    a = b                           a[  7] = b
    a = b                           a[  8] = b
(defalias 'verilog-insert-indices #[(max) "\301\302\"\207" [max verilog-insert-1 "[%3d]"] 3 (#$ . 123722) "NMAX: "])
#@764 Insert a set of generated numbers into a rectangle.
The upper left corner is defined by point.  The numbers are padded to three
digits, starting with 000 and extending to (MAX - 1).  If no prefix argument
is supplied, then the user is prompted for the MAX number.  Consider the
following code fragment:

buf buf                             buf buf000
    buf buf                             buf buf001
    buf buf                             buf buf002
    buf buf                             buf buf003
    buf buf   ==> generate-numbers ==>  buf buf004
    buf buf                             buf buf005
    buf buf                             buf buf006
    buf buf                             buf buf007
    buf buf                             buf buf008
(defalias 'verilog-generate-numbers #[(max) "\301\302\"\207" [max verilog-insert-1 "%3.3d"] 3 (#$ . 124601) "NMAX: "])
#@110 Mark the current Verilog function (or procedure).
This puts the mark at the end, and point at the beginning.
(defalias 'verilog-mark-defun #[nil "\300 \207" [mark-defun] 1 (#$ . 125491) nil])
#@438 Put the region into a Verilog comment.
The comments that are in this area are "deformed":
`*)' becomes `!(*' and `}' becomes `!{'.
These deformed comments are returned to normal if you use
\[verilog-uncomment-region] to undo the commenting.

The commented area starts with `verilog-exclude-str-start', and ends with
`verilog-exclude-str-end'.  But if you change these variables,
\[verilog-uncomment-region] won't recognize the comments.
(defalias 'verilog-comment-region #[(start end) "\212b\210\212\305\306w\210l)\203�\212\305\306x\210n)\204�\307y\210\202!�\310 \210	c\210`\311 \210\nb\210\310 \210c\210\311 \210b\210\212\312\313\n\314#\203J�\315\316\314\211#\210\2029�)\212\nT\312\317\f\314#\205`�\315\320\314\211#\210\202O�+\207" [end verilog-exclude-str-end start verilog-exclude-str-start s+1 " 	" nil 1 beginning-of-line newline re-search-backward "\\*/" t replace-match "*-/" "/\\*" "/-*"] 4 (#$ . 125690) "r"])
#@175 Uncomment a commented area; change deformed comments back to normal.
This command does nothing if the pointer is not in a commented
area.  See also `verilog-comment-region'.
(defalias 'verilog-uncomment-region #[nil "\212``\212\305\n\306\307#\210`\310\306\307#\210`)	`\232\204#�`X\203)�\311\312!\202p�b\210\313 \210`\306\210\f`T|\210)\212\314\315	\307#\203L�\316\317\307\211#\210\202;�)\212\314\320	\307#\203_�\316\321\307\211#\210\202N�)	b\210\313 \210`\306\210\f`T|)+\207" [end start verilog-exclude-str-start verilog-exclude-str-end pos search-backward nil t search-forward message "Not standing within commented area." beginning-of-line re-search-backward "\\*-/" replace-match "*/" "/-\\*" "/*"] 4 (#$ . 126623) nil])
#@70 Move backward to the beginning of the current function or procedure.
(defalias 'verilog-beg-of-defun #[nil "\305\306\307\310\n	#\203,�\311 \211\203,�\312 \203,�\313\n\203(�`\nV\202)�\314\204�\315\f!\210\316\225,\207" [verilog-defun-re NOERROR BOUND REGEXP mdata nil move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0] 4 (#$ . 127363) nil])
#@97 Move backward to the beginning of the current function or procedure.
Uses `verilog-scan' cache.
(defalias 'verilog-beg-of-defun-quick #[nil "\305\306\305\f\204+�\307\n	#\203+�\310\311\224!\203$�\307\312\305\313#\210\202�\311\224\211\203\f�\f,\207" [verilog-defun-re noerror bound regexp pt nil move re-search-backward verilog-inside-comment-or-string-p 0 "[/\"]" t] 4 (#$ . 127783) nil])
#@63 Move forward to the end of the current function or procedure.
(defalias 'verilog-end-of-defun #[nil "\305\306\307\310\n	#\203,�\311 \211\203,�\312 \203,�\313\n\203(�`\nW\202)�\314\204�\315\f!\210\316\225,\207" [verilog-end-defun-re NOERROR BOUND REGEXP mdata nil move (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) t store-match-data 0] 4 (#$ . 128185) nil])
(defalias 'verilog-get-end-of-defun #[nil "\212\305\306\305\f\204,�\307\n	#\203,�\310\311\224!\203%�\307\312\305\306#\210\202	�\311\225\211\203
�\f,\2035�`\202<�\313\314\315 \"\210d)\207" [verilog-end-defun-re noerror bound regexp pt nil t re-search-forward verilog-inside-comment-or-string-p 0 "[/\"\n]" error "%s: Can't find endmodule" verilog-point-text] 4])
#@78 Label matching begin ... end, fork ... join and case ... endcase statements.
(defalias 'verilog-label-be #[nil "\306\307`\310 \210\311 \312 \210\311 \313	!b\210	Z\314V\203#�\315\316!\210\313!`V\203\225�
\307\317 !\320\"\321! #\203b�\322 \211\"\203b�\323 \203b�\324\" \203^�` W\202_�\325\2047�\326\"!\210\306\225,\203\225�\306\224b\210\327 #\330#\325\"\210\307\210\331 \210)\fT\211\332\246\333U\203#�\315\334\f\"\210\202#�\nb\210	Z\314V\204\246�\f\335V\205\252�\315\336\f\"-\207" [e b oldpos case-fold-search cnt verilog-auto-end-comment-lines-re 0 nil verilog-beg-of-defun point-marker verilog-end-of-defun marker-position 200 message "Relabeling module..." move (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) t store-match-data verilog-indent-line verilog-set-auto-endcomments delete-horizontal-space 10 9 "%d..." 20 "%d lines auto commented" NOERROR BOUND REGEXP mdata indent-str] 6 (#$ . 128969) nil])
#@42 Move backward to beginning of statement.
(defalias 'verilog-beg-of-statement #[nil "\306o\204~�\307\310!\204~�h\311U\204~�\307\312!\204~�\307\313!\204$�\314\315!\203~�\307\316!\203D�`\212\317 \210\307	!\203>�\307\n!\204>�`)b\204~�\307!\203c�`\307
!\203]�`\317 \210\f`U\203L�\fb)\204~�\307!\204~�\212\317 \210\307\n!)\204~�\320 \210\317 \210\202�\321 \210\307!\205\216�\322\225b\210\321 )\207" [h verilog-label-re verilog-end-block-re verilog-complete-reg p verilog-extended-complete-re nil looking-at "`\\w+" 59 "\\w+\\W*:\\W*\$coverpoint\\|cross\\|constraint\$" "\\<" forward-word-strictly -1 "\$\\w+\\W*:\\W*\$?\$\\<\\(assert\\|assume\\|cover\$\\>\\s-+\\<property\\>\\)\\|\$\\<assert\\>\$" verilog-backward-token verilog-backward-syntactic-ws verilog-forward-syntactic-ws 0 verilog-basic-complete-re verilog-preprocessor-re] 2 (#$ . 129947) nil])
#@42 Move backward to beginning of statement.
(defalias 'verilog-beg-of-statement-1 #[nil "\303 \203�\304 \210`\30529�\306	!?\2058�`\304 \210n\204-�h\307U\204-�\310 \210\306\n!\203�b\210\311\305\312\"\210\202�0\210\313 )\207" [pt verilog-complete-reg verilog-ends-re verilog-in-comment-p verilog-backward-syntactic-ws done looking-at 59 verilog-backward-token throw t verilog-forward-syntactic-ws] 3 (#$ . 130822) nil])
#@43 Move forward to end of current statement.
(defalias 'verilog-end-of-statement #[nil "\306\307\310 \203�\311y\210\312u\202\376�\313\n!\203�\314 \202\376�\307f\315\232\203(�\307u\202\376�\3161\213�\3172\205�\320\311!\210\321 \210l\203>�\311y\210\313\322!\203S�\323\307w\210\311u\210\324\317`\"\210\2020�\212\320\312!\210\313\n!)\203k�\306\224b\210\324\317\307\"\210\2020�\313\325!\203y�\324\317`\"\210\2020�m\2030�\324\317`\"\210\2020�\2110\202\220�\210\307\202\376�\205\376�\204\375�\3172\376�\307\326\327\330
\f#\203\314�\331 \211\203\314�\321 \203\314�\332
\203\310�`
W\202\311�\333\204\245�\334!\210\306\225,\210\311\225\203\337�	T\202\341�	Sm\203\356�\324\317`\"\210\202\233�	\306U\203\233�\324\317\335 \"\210\202\233�*\207" [pos nest verilog-beg-block-re verilog-end-statement-re NOERROR BOUND 0 nil verilog-in-directive-p 1 -1 looking-at verilog-forward-sexp 125 (error) found forward-sexp verilog-skip-forward-comment-or-string "[ 	]*;" "^;" throw "[ 	]*)" move (nil nil) re-search-forward match-data (nil nil) t store-match-data verilog-end-of-statement REGEXP mdata] 4 (#$ . 131249) nil])
#@87 Return true if in a case region.
More specifically, point @ in the line foo : @ begin
(defalias 'verilog-in-case-region-p #[nil "\212\305 \210\306\307!\205x�\310 \210h\311U\205x�\3122x�\313\314\315\316\317\320\n	#\203E�\321 \211\203E�\322 \203E�\323\n\203A�`\nV\202B�\324\204!�\325\f!\210\326\225,\210\327\225\203X�T\202�\330\225\203n�\313U\203h�\331\312\313\"\210S\202�\331\312\326U\"\210\202�)\207" [nest NOERROR BOUND REGEXP mdata verilog-forward-syntactic-ws looking-at "\\<begin\\>" verilog-backward-syntactic-ws 58 found 1 "\$\\<module\\>\$\\|\$\\<randcase\\>\\|\\<case[xz]?\\>[^:]\$\\|\$\\<endcase\\>\$\\>" nil move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0 3 2 throw] 4 (#$ . 132375) nil])
#@49 Call `backward-up-list' ARG, ignoring comments.
(defalias 'verilog-backward-up-list #[(arg) "\302\303	!)\207" [parse-sexp-ignore-comments arg t backward-up-list] 2 (#$ . 133171)])
#@43 Call `forward-sexp' ARG, inside comments.
(defalias 'verilog-forward-sexp-cmt #[(arg) "\302\303	!)\207" [parse-sexp-ignore-comments arg nil forward-sexp] 2 (#$ . 133358)])
#@45 Call `forward-sexp' ARG, ignoring comments.
(defalias 'verilog-forward-sexp-ign-cmt #[(arg) "\302\303	!)\207" [parse-sexp-ignore-comments arg t forward-sexp] 2 (#$ . 133537)])
#@101 Return true if in a generate region.
More specifically, after a generate and before an endgenerate.
(defalias 'verilog-in-generate-region-p #[nil "\305\212\3062l�\307U?\205k�\310\311\312\313\314\n	#\203:�\315 \211\203:�\316 \203:�\317\n\2036�`\nV\2027�\320\204�\321\f!\210\307\225,\205k�\305\225\203P�\322\306\305\"\202e�\323\225\203\\�S\211\202e�\324\225\205k�T\211\205k�\202�0\210)\307U)\207" [nest NOERROR BOUND REGEXP mdata 1 done 0 "\\<\$module\$\\|\$generate\$\\|\$endgenerate\$\\>" nil move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data throw 2 3] 4 (#$ . 133721) nil])
#@41 Return true if between a fork and join.
(defalias 'verilog-in-fork-region-p #[nil "\212\306 \210`)\307\212\310U\204^�\311	\312\313\314\f\n#\203<�\315 \211\203<�\316 \203<�\317\2038�`V\2029�\320\204�\321
!\210\310\225,\203^�\307\225\203R�S\211\202[�\322\225\203^�T\211\204\n�)\310U*\207" [nest lim NOERROR BOUND REGEXP mdata verilog-beg-of-defun 1 0 "\\<\$fork\$\\|\$join\\(_any\\|_none\$?\\)\\>" move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data 2] 4 (#$ . 134389) nil])
#@65 Return true if inside an `assert/assume/cover final' statement.
(defalias 'verilog-in-deferred-immediate-final-p #[nil "\300\301!\205\n�\302\303\304\"\207" [looking-at "final" verilog-looking-back "\\<\$?:assert\\|assume\\|cover\$\\>\\s-+" nil] 3 (#$ . 134952) nil])
#@74 Skip backward to nearest enclosing case item.
Limit search to point LIM.
(defalias 'verilog-backward-case-item #[(lim) "\306\212	\307\310\311\f\n#\203.�\312 \211\203.�\313 \203.�\314\203*�`V\202+�\315\204\n�\316
!\210\317\225,\210`)$%\212\320\321$\315#)\205N\317\306\211&'((\322W\203\303�\323$\307\310\311\f\n#\203\204�\312 \211\203\204�\313 \203\204�\314\203\200�`V\202\201�\315\204`�\316
!\210\317\225,\203\303�\322\225\203\247�(T\211(\317Y\203P�\324\325\326 \"\210\202P�\327\225\203\265�(S\211(\202R�\330\225\203P�(T\211(\202R�\331\306x\210\313 \210`&\332\306\307\310\311\f\n#\203\371�\312 \211\203\371�\313 \203\371�\314\203\365�`V\202\366�\315\204\325�\316
!\210\317\225,\203*\322\225\203\322\225b\210\333 \210\334\335!\203\336 \210\333 \210`\202-\317\225b\210\333 \210`\202-\324\337!\211'&{%\340\341%\"\211&\203K\342%\317&#\343P%%+*\207" [verilog-endcomment-reason-re lim NOERROR BOUND REGEXP mdata nil move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0 search-backward ":" 1 "\$\\[\$\\|\$\\]\$\\|\$:\$" error "%s: unbalanced [" verilog-point-text 2 3 "	 " "\\<\$randcase\\|case[zx]?\$\\>\\|;\\|\\<end\\>" verilog-forward-ws&directives looking-at "(" forward-sexp "Malformed case item" string-match "[ 	]*\$\\(\n\$\\|\$//\$\\|\$/\\*\$\\)" substring "..." lim1 str e b colon] 6 (#$ . 135227) nil])
#@33 Kill auto comment on this line.
(defalias 'verilog-kill-existing-comment #[nil "\212\302\210`\303 \210\304\305\306#\211\205�	\307Z|+\207" [e b nil beginning-of-line search-forward "//" t 2] 5 (#$ . 136676)])
(defconst verilog-directive-nest-re "\$`else\\>\$\\|\$`endif\\>\$\\|\$`if\\>\$\\|\$`ifdef\\>\$\\|\$`ifndef\\>\$\\|\$`elsif\\>\$")
#@383 Add ending comment with given INDENT-STR.
With KILL-EXISTING-COMMENT, remove what was there before.
Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
Insert `// case expr ' if this line ends a case block.
Insert `// ifdef FOO ' if this line ends code conditional on FOO.
Insert `// NAME ' if this line ends a function, task, module,
primitive or interface named NAME.
(defalias 'verilog-set-auto-endcomments #[(indent-str kill-existing-comment) "\212\306\307!\203\204�\212\310\210\311\312\313 \314#)\204\315\310\211\211\316\225\203&�\317\202'�\320\310\210\2036�\321 \210\322 \210\212\323\315!\210
\324U\204\332�@\310\325ABC\326D\327CBA#\203|�\330 \211D\203|�\331 \203|�\332DB\203x�`BV\202y�\314\204Q�\333D!\210\324\225,\203\332�\315\225\203\227�
\315U\203>�\317\202>�\316\225\203\243�
T\211\202?�\334\225\203\257�
S\211\202?�\335\225\203\273�
S\211\202?�\336\225\203\307�
S\211\202?�\337\225\203>�
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S\202\211\316\225\203\342
T\202\211\334\225\203

\324U\203\211\324\225b\210`L\310J\361 I\201U�IPI\201V�\377\315\"\210\202\211\335\225\203\211
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S\202P\316\225\203\251
T\202P\334\225\203\324
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T\202\323\316\225\203\323
S\211\324W\203\323\324\225b\210\310\211\340\310w\210\201_� \210`\342\310w\210`\f{R*\201V�\377\315\"\210\202\3230\210)\310\210\203}\321 \210\322 \210\344RPc+\202N\310\211\211SQR\310\210\203\245\330 T\201`�\216\321 \210*\322 \210\323 \210\336\225\203\275\201a�Q\201b�S\202m\337\225\203\317\201c�Q\201b�S\202m\201d�\225\203\336\201e�Q\202m\201f�\225\203\355\201g�Q\202m\201h�\225\203\374\201i�Q\202m\201j�\225\203\201k�Q\202m\201\\�\225\203\201l�Q\202m\201m�\225\203)\201n�Q\202m\201o�\225\2038\201p�Q\202m\201q�\225\203G\201r�Q\202m\201s�\225\203V\201t�Q\202m\201u�\225\203e\201v�Q\202m\201w�\201x�!\210\310\211\212Q\310\325ABC\326D\327CBA#\203\252\330 \211D\203\252\331 \203\252\332DB\203\246`BV\202\247\314\204\333D!\210\324\225,\210\315\225\203;\340\310w\210\201_� \210\306\201y�!\203\322\324\225b\210\201_� \210S\203+S\310\325ABC\201z�D\201{�CBA#\203\330 \211D\203\201|� \203\201}�DB\203`BW\202\314\204\346\333D!\210\324\225,\203+\324\224b\210\201_� \210`\342\310w\210`\f{R\202D\346\314!\210\201~�R+\310\210\344RPc+))\207" [kill-existing-comment else m e b nest looking-at "\$`endif\$\\|\$`else\$" nil search-backward "//" line-beginning-position t 1 2 "!" " " verilog-kill-existing-comment delete-horizontal-space backward-sexp 0 move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) store-match-data 3 4 5 6 "^ 	" verilog-forward-syntactic-ws "a-zA-Z0-9_" count-lines " // " " // unmatched `else, `elsif or `endif" ding "\\<end" declaration "\$" "\$[ 	]*:" "UNMATCHED!!" verilog-leap-to-head "\\<randcase\\>" "randcase" "\$\\(unique0?\\s-+\\|priority\\s-+\$?case[xz]?\\)" match-string verilog-get-expr " // UNMATCHED !!" verilog-beg-of-defun search-forward ":" " // block: " verilog-in-case-region-p verilog-backward-case-item " // case: " verilog-beg-of-statement "" verilog-continued-line "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>" "\$\\<begin\\>\$\\|\$\\<end\\>\$\\|\$\\<if\\>\$\\|\$assert\$" skip verilog-directive-nest-re NOERROR BOUND REGEXP mdata verilog-minimum-comment-distance indent-str type verilog-end-block-ordered-re str err cntx there here lim verilog-named-block-re verilog-endcomment-reason-re reg string name-re save-match-data-internal " // else: !if" throw " // else: !assert " verilog-in-fork-region-p " // fork branch" "\\<end\\>" forward-word-strictly 11 "\\<\$\\(class\$\\|\$endclass\$\\|\$package\\|primitive\\|\\(macro\$?module\\)\\)\\>" "unmatched endclass" verilog-forward-ws&directives #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] "\$\\<function\\>\$\\|\$\\<\\(endfunction\\|task\\|\\(macro\$?module\\|primitive\\)\\>\\)" "\\w+\$?:\n\\|\\s-\$*[(;]" "\$\\<task\\>\$\\|\$\\<\\(endtask\\|function\\|\\(macro\$?module\\|primitive\\)\\>\\)" 7 "\$\\<\\(macro\$?module\\>\\)\\|\\<endmodule\\>" 8 "\$\\<primitive\\>\$\\|\$\\<\\(endprimitive\\|package\\|interface\\|\\(macro\$?module\\)\\>\\)" 9 "\$\\<interface\\>\$\\|\$\\<\\(endinterface\\|package\\|primitive\\|\\(macro\$?module\\)\\>\\)" 10 "\$\\<package\\>\$\\|\$\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\$?module\\)\\>\\)" "\$\\<class\\>\$\\|\$\\<\\(endclass\\|primitive\\|interface\\|\\(macro\$?module\\)\\>\\)" 12 "\$\\<covergroup\\>\$\\|\$\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\$?module\\)\\>\\)" 13 "\$\\<program\\>\$\\|\$\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\$?module\\)\\>\\)" 14 "\$\\<\\(rand\$?sequence\\>\\)\\|\$\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\$?module\\)\\>\\)" 15 "\$\\<clocking\\>\$\\|\\<endclocking\\>" 16 "\$\\<property\\>\$\\|\\<endproperty\\>" error "Problem in verilog-set-auto-endcomments" "static\\|automatic" (nil nil) re-search-forward verilog-skip-forward-comment-or-string (nil nil) "unmatched end(function|task|module|primitive|interface|package|class|clocking)"] 7 (#$ . 137039)])
#@57 Grab expression at point, e.g., case ( a | b & (c ^d)).
(defalias 'verilog-get-expr #[nil "\306 \210\307\310w\210`\311\312\313!\203x�\311u\210\306 \210\312\314!\203t�\311u\210	\315U\204t�\316\310\317\320\321\f\n#\203R�\322 \211\203R�\323 \203R�\324\203N�`W\202O�\325\204.�\326
!\210\315\225,\203t�\311\225\203h�	T\211\202!�\327\225\203 �	S\211\202!�`\202P\312\314!\203\331�\311u\210	\315U\204\325�\316\310\317\320\321\f\n#\203\263�\322 \211\203\263�\323 \203\263�\324\203\257�`W\202\260�\325\204\217�\326
!\210\315\225,\203\325�\311\225\203\311�	T\211\202\202�\327\225\203\201�	S\211\202\202�`\202P\312\330!\203A\311u\210	\315U\2046\331\310\317\320\321\f\n#\203\322 \211\203\323 \203\324\203`W\202\325\204\360�\326
!\210\315\225,\2036\311\225\203*	T\211\202\343�\327\225\203\342�	S\211\202\343�\306 \210\332\310w\210`\202P\312\333!\203K\202P\334\310w\210`)!!{\"\335\336\"\"\211!\203o\337\"\315!#\340P\"\"+\207" [b par NOERROR BOUND REGEXP mdata verilog-forward-syntactic-ws " 	" nil 1 looking-at "@" "(" 0 "\$(\$\\|\$)\$" move (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) t store-match-data 2 "\\[" "\$\\[\$\\|\$\\]\$" "^ 	\n\f" "/[/\\*]" "^: 	\n\f" string-match "[ 	]*\$\\(\n\$\\|\$//\$\\|\$/\\*\$\\)" substring "..." e str] 5 (#$ . 144552)])
#@128 Take a signal vector on the current line and expand it to multiple lines.
Useful for creating tri's and other expanded fields.
(defalias 'verilog-expand-vector #[nil "\300\301\302\"\207" [verilog-expand-vector-internal "[" "]"] 3 (#$ . 145926) nil])
#@85 Given BRA, the start brace and KET, the end brace, expand one line into many lines.
(defalias 'verilog-expand-vector-internal #[(bra ket) "\212\306y\210`\307\210`{\310\311\312	!\313\312\n!\314\260\"\205\325�\315\316\"\317\315\320\"!\321\224\321\225U\2034�\f\202>�\317\322\321\224T\321\225#!\323\224\323\225U\203K�\316\202V�\317\322\320\323\224\\\323\225#!\315\324\"\307\211\306W\203y�\f
[)
\fW\203\225�
\fX\203\254�\325\fC\"\fZ\202�\f
X\203\254�\325\fC\"\f\\\211\202\226�`\306y\210`|\210\203\320�	\326@!\n\327\260c\210A\211\204\270�\330\331!.*\207" [signal-string bra ket sig-head vec-start vec-end 0 nil string-match "\$.*\$" regexp-quote "\$[0-9]*\$\$:[0-9]*\\|\$\$::[0-9---]*\\|\$" "\$.*\$$" match-string 1 string-to-number 2 3 substring 4 5 append int-to-string "\n" delete-char -1 vec-range sig-tail vec tmp] 7 (#$ . 146182)])
#@43 Strip all comments from the Verilog code.
(defalias 'verilog-strip-comments #[nil "eb\210\301\302\303\304#\203;�\305\306\307 `\"8\203�\301\310\303\304#\210\202�\311 \203,�\301\312\303\304#\210\202�`\313Z\303\210`|\210)\202�eb\210\301\314\303\304#\205i�\305\306\307 `\"8\203Y�\301\310\303\304#\210\202>�`\313Z\301\312!\210`|\210)\202>�\207" [bpt re-search-forward "//" nil t 3 parse-partial-sexp line-beginning-position "\"" verilog-in-star-comment-p "\\*/" 2 "/\\*"] 4 (#$ . 147090) nil])
#@58 Convert structural Verilog instances to occupy one line.
(defalias 'verilog-one-line #[nil "eb\210\300\301\302\303#\205�\304\305\302\211#\210\202�\207" [re-search-forward "\$[^;]\$[ 	]*\n[ 	]*" nil t replace-match "\\1 "] 4 (#$ . 147594) nil])
#@53 Return name of linter, either surelint or verilint.
(defalias 'verilog-linter-name #[nil "\306\307\310\211\311\312
	#\203*�\313\f\n	$\211G\311\224\fG\\^\202
�	.\306\307\310\211\311\312
	#\203X�\313\f\n	$\211G\311\224\fG\\^\202;�	.\211\314\267\202m�\315\202}�\316\202}�\317\267\202|�\315\202}�\316\202}�\315*\207" [compile-command string literal fixedcase to-string from-string "\\s .*$" "" nil 0 string-match replace-match #s(hash-table size 2 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("surelint" 101 "verilint" 105)) surelint verilint #s(hash-table size 2 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("surelint" 116 "verilint" 120)) start verilog-linter lint-word1 compile-word1] 7 (#$ . 147848)])
#@351 Convert a Verilog linter warning line into a disable statement.
For example:
	pci_bfm_null.v, line  46: Unused input: pci_rst_
becomes a comment for the appropriate tool.

The first word of the `compile-command' or `verilog-linter'
variables is used to determine which product is being used.

See \[verilog-surelint-off] and \[verilog-verilint-off].
(defalias 'verilog-lint-off #[nil "\301 \211\302\267\202�\303 \202�\304 \202�\305\306!)\207" [linter verilog-linter-name #s(hash-table size 2 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (surelint 9 verilint 14)) verilog-surelint-off verilog-verilint-off error "Linter name not set"] 3 (#$ . 148640) nil])
#@281 Convert a SureLint warning line into a disable statement.
Run from Verilog source window; assumes there is a *compile* buffer
with point set appropriately.

For example:
	WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
becomes:
	// surefire lint_line_off UDDONX
(defalias 'verilog-surelint-off #[nil "\306\300!\203\n�\202�	\307\n!\205\333�\212\310\n!\210\311 \210\312\313!\205\332�\314\315!\314\316!\314\317!\320\f!)\321\211*+)\204y�\322\f!\205E�\323\f!\211)\204y�\324,\325\326\327\330\f\"*\f\324$!-\331-!\203k�\325+-\"-\322-!\205v�\323-!)*\310)!\210eb\210\332
![y\210\321\210\3332\330�\334 \203\301�\335\336!\210\312\337!\203\275�\340\225b\210\341 .\342.\343#\203\265�\344\333\324\"\202\271�\345Pc)\202\327�\324\202\327�\346 \203\322�\335\347!\210\327\350\"c\202\327�\327\350\"c0.))\207" [next-error-last-buffer compilation-last-buffer buff code file line boundp buffer-live-p switch-to-buffer beginning-of-line looking-at "\$INFO\\|WARNING\\|ERROR\$ \\[[^-]+-\$[^]]+\$\\]: \$[^,]+\$, line \$[0-9]+\$: \$.*\$$" match-string 2 3 4 get-file-buffer nil file-exists-p find-file-noselect t expand-file-name read-file-name format "Find this error in: (default %s) " file-directory-p string-to-number already verilog-in-slash-comment-p re-search-backward "//" "// surefire lint_off_line " 0 line-end-position re-search-forward move throw " " verilog-in-star-comment-p "/\\*" " // surefire lint_off_line %6s" buffer dir filename pop-up-windows name lim] 7 (#$ . 149326) nil])
#@185 Convert a Verilint warning line into a disable statement.

For example:
	(W240)  pci_bfm_null.v, line  46: Unused input: pci_rst_
becomes:
	//Verilint 240 off // WARNING: Unused input
(defalias 'verilog-verilint-off #[nil "\212\300 \210\301\302!\205�\303\304\305\306\307!\"!\210\300 \210\310 )\207" [beginning-of-line looking-at "\$.*\$([WE]\$[0-9A-Z]+\$).*,\\s +line\\s +[0-9]+:\\s +\$[^:\n]+\$:?.*$" replace-match format "\\1//Verilint %3s off // WARNING: \\3" match-string 2 verilog-indent-line] 5 (#$ . 150860) nil])
#@71 Update automatics with \[verilog-auto], save the buffer, and compile.
(defalias 'verilog-auto-save-compile #[nil "\301 \210\302 \210\303!\207" [compile-command verilog-auto save-buffer compile] 2 (#$ . 151394) nil])
#@217 Preprocess the buffer, similar to `compile', but put output in Verilog-Mode.
Takes optional COMMAND or defaults to `verilog-preprocessor', and
FILENAME to find directory to run in, or defaults to `buffer-file-name'.
(defalias 'verilog-preprocess #[(&optional command filename) "\204�\306	!\307\302!\205�\n\310\f\206�
!\311\312R r\313\314!q\210p\315 \210 \316\211!\317\211\"\317#$\320 \210\321\322!\210+\211%&r\323\314!q\210\324\325Qc\210\326'\316\317\316(&\210\327 \210\330\331!?\205z�\205z�\332\333! )\334%!\210.\207" [command verilog-preprocessor font-lock-mode fontlocked filename buffer-file-name verilog-expand-command boundp file-name-directory "cd " "; " get-buffer-create "*Verilog-Preprocessed*" kill-all-local-variables nil t erase-buffer run-hooks temp-buffer-setup-hook get-buffer "// " "\n" call-process verilog-mode fboundp font-lock-ensure intern "font-lock-fontify-buffer" internal-temp-output-buffer-show dir cmd default-directory #1=#:old-dir buffer-read-only buffer-undo-list inhibit-modification-hooks inhibit-read-only #2=#:buf standard-output shell-file-name shell-command-switch] 8 (#$ . 151618) (list (let ((default (verilog-expand-command verilog-preprocessor))) (set (make-local-variable 'verilog-preprocessor) (read-from-minibuffer "Run Preprocessor (like this): " default nil nil 'verilog-preprocess-history default))))])
#@63 Print a warning with `format' using STRING and optional ARGS.
(defalias 'verilog-warn #[(string &rest args) "\302\303\304P	#\207" [string args apply message "%%Warning: "] 4 (#$ . 153010)])
#@111 Call `error' using STRING and optional ARGS.
If `verilog-warn-fatal' is non-nil, call `verilog-warn' instead.
(defalias 'verilog-warn-error #[(string &rest args) "\203\n�\303\304	\n#\207\303\305	\n#\207" [verilog-warn-fatal string args apply error verilog-warn] 4 (#$ . 153208)])
#@128 Execute BODY and add error prefix to any errors found.
This lets programs calling batch mode to easily extract error messages.
(defalias 'verilog-batch-error-wrapper '(macro . #[(&rest body) "\301\302\303\304\305B\306BBBE\207" [body let ((verilog-warn-fatal nil)) condition-case err progn ((error (error "%%Error: %s%s" (error-message-string err) (if (featurep 'xemacs) "\n" ""))))] 6 (#$ . 153496)]))
#@125 Internal processing of a batch command.
Runs FUNREF on all command arguments.
Save the result unless optional NO-SAVE is t.
(defalias 'verilog-batch-execute-func #[(funref &optional no-save) "\306\3071)�\306\310\301\306\"\210\311\211\306\310\312\313\"\210\314 \315\316
\"\210\315\317
\")0\2024�\320\321\322!\323#))\207" [verilog-warn-fatal make-backup-files enable-local-variables enable-local-eval create-lockfiles orig-buffer-list nil (error) set-default t major-mode verilog-mode buffer-list mapc #[(buf) "\302!\205 �rq\210\303\301!\210\304 \305\301\306\307#\210\310 \210\311 \210\312 )\207" [buf verilog-batch-orig-buffer-string buffer-file-name make-local-variable buffer-string put permanent-local t verilog-mode verilog-auto-reeval-locals verilog-getopt-flags] 4] #[(buf) "\304!\205;�\212\305\304!!\204�\306\307\304!\"\210\310\311\304!\"\210q\210	 \210\312 \210\n?\205:�\313 \205:�\314 \232?\205:�\315 )\207" [buf funref no-save verilog-batch-orig-buffer-string buffer-file-name file-exists-p error "File not found: %s" message "Processing %s" verilog-star-cleanup buffer-modified-p buffer-string save-buffer] 4] error "%%Error: %s%s" error-message-string "" err] 5 (#$ . 153906)])
#@317 For use with --batch, perform automatic expansions as a stand-alone tool.
This sets up the appropriate Verilog mode environment, updates automatics
with \[verilog-auto] on all command-line files, and saves the buffers.
For proper results, multiple filenames need to be passed on the command
line in bottom-up order.
(defalias 'verilog-batch-auto #[nil "\204�\301\302!\210\303\304!\207" [noninteractive error "Use verilog-batch-auto only with --batch" verilog-batch-execute-func verilog-auto] 2 (#$ . 155122)])
#@225 For use with --batch, perform automatic deletion as a stand-alone tool.
This sets up the appropriate Verilog mode environment, deletes automatics
with \[verilog-delete-auto] on all command-line files, and saves the buffers.
(defalias 'verilog-batch-delete-auto #[nil "\204�\301\302!\210\303\304!\207" [noninteractive error "Use verilog-batch-delete-auto only with --batch" verilog-batch-execute-func verilog-delete-auto] 2 (#$ . 155641)])
#@241 For use with --batch, perform whitespace deletion as a stand-alone tool.
This sets up the appropriate Verilog mode environment, removes
whitespace with \[verilog-delete-trailing-whitespace] on all
command-line files, and saves the buffers.
(defalias 'verilog-batch-delete-trailing-whitespace #[nil "\204�\301\302!\210\303\304!\207" [noninteractive error "Use verilog-batch-delete-trailing-whitespace only with --batch" verilog-batch-execute-func verilog-delete-trailing-whitespace] 2 (#$ . 156089)])
#@356 For use with --batch, perform automatic differences as a stand-alone tool.
This sets up the appropriate Verilog mode environment, expand automatics
with \[verilog-diff-auto] on all command-line files, and reports an error
if any differences are observed.  This is appropriate for adding to regressions
to insure automatics are always properly maintained.
(defalias 'verilog-batch-diff-auto #[nil "\204�\301\302!\210\303\304\305\"\207" [noninteractive error "Use verilog-batch-diff-auto only with --batch" verilog-batch-execute-func verilog-diff-auto t] 3 (#$ . 156598)])
#@327 For use with --batch, perform automatic injection as a stand-alone tool.
This sets up the appropriate Verilog mode environment, injects new automatics
with \[verilog-inject-auto] on all command-line files, and saves the buffers.
For proper results, multiple filenames need to be passed on the command
line in bottom-up order.
(defalias 'verilog-batch-inject-auto #[nil "\204�\301\302!\210\303\304!\207" [noninteractive error "Use verilog-batch-inject-auto only with --batch" verilog-batch-execute-func verilog-inject-auto] 2 (#$ . 157178)])
#@206 For use with --batch, reindent an entire file as a stand-alone tool.
This sets up the appropriate Verilog mode environment, calls
\[verilog-indent-buffer] on all command-line files, and saves the buffers.
(defalias 'verilog-batch-indent #[nil "\204�\301\302!\210\303\304!\207" [noninteractive error "Use verilog-batch-indent only with --batch" verilog-batch-execute-func verilog-indent-buffer] 2 (#$ . 157728)])
(defconst verilog-indent-alist '((block + ind verilog-indent-level) (case + ind verilog-case-indent) (cparenexp + ind verilog-indent-level) (cexp + ind verilog-cexp-indent) (defun . verilog-indent-level-module) (declaration . verilog-indent-level-declaration) (directive verilog-calculate-indent-directive) (tf . verilog-indent-level) (behavioral + verilog-indent-level-behavioral verilog-indent-level-module) (statement . ind) (cpp . 0) (comment verilog-comment-indent) (unknown . 3) (string . 0)))
#@102 Return true if this is a continued line.
Set point to where line starts.  Limit search to point LIM.
(defalias 'verilog-continued-line-1 #[(lim) "\302\303y\304=\203�\305\210\306	!\210o\203�\305\202!�\307 \202!�\305)\207" [continued lim t -1 0 nil verilog-backward-ws&directives verilog-backward-token] 2 (#$ . 158649)])
#@257 Calculate the indent of the current Verilog line.
Examine previous lines.  Once a line is found that is definitive as to the
type of the current line, return that lines' indent level and its type.
Return a list of two elements: (INDENT-TYPE INDENT-LEVEL).
(defalias 'verilog-calculate-indent #[nil "\212`\306\307\310\311!\212\312\306\313@\314A\315@
\f#\203=�\316 \211A\203=�\317 \203=�\320A
\2039�`
V\202:�\313\204�\321A!\210\307\225-B\306C\3222\277\323 \203X�\324\322\325\"\210\212\326 \210\310D!\205m�\310\327!\206l�\310\330!?)\203v�\324\322\331\"\210\332 \211C\203\231�C\307V\203\215�\324\322\333\"\210\202\231�C\307U\203\231�\324\322\334\"\210E\203\257�\335 \203\257�\336 \204\257�\337\324\322\334\"\210o\203\270�\324\322\340\"\210\341B!\203,\336 \203\313�\310F!\203,`G\310H!\204\350�\341B!\203\350�Gb\210\324\322\342\"\210\202\354�Gb\210\336 \203\310F!\203\326 \210\343\306w\210\324\322\344\"\210\203#I\204#\310J!\203#\326 \210\343\306w\210\324\322\345\"\210\202(\324\322\342\"\210)\202/b\210\310\346!\203\263\337KL\306\347@\314A\315@
\f#\203j\316 \211A\203j\317 \203j\320A
\203f`
V\202g\313\204C\321A!\210\307\225,\203\262\337\225\203\202KTK\2028\350\225\203\255KS\211K\307U\2038M\203\237\324\322\345\"\210\2028\326 \210\351 \210\324\322\345\"\210\2028\352\225\203\321KSK\353 \210\310N!\203\311\324\322\345\"\210\2028\324\322\334\"\210\2028\306\337OP\354\225\203\342\355P\202B\356\225\203\355\357P\202B\360\225\203\370\361P\202B\362\225\203\363P\202B\364\225\203\365P\202B\366\225\203\367P\202B\370\225\203$\371P\202B\372\225\203/\373P\202B\374\225\203:\375P\202B\376\225\203B\377P\201R�2\255P\306\347@\314A\315@
\f#\203z\316 \211A\203z\317 \203z\320A
\203v`
V\202w\313\204S\321A!\210\307\225,\205\254\337\225\203\237OS\211O\307U\203H\324\201R�\337\"\210\202H\350\225\203HOTO\202H0\210*\2028)\324\322\201S� \"\210\202\257�0\211Q\204\310\340Q\n\307V\203\326\201T�\nD\202Q\201U�\267\202Q\201V� D\202QiD\202Q\307D\202\334iD\202\334CD\202Q\201W� D.\207" [starting_position case-fold-search par begin NOERROR BOUND nil 0 looking-at "[ 	]*begin\\>" "\$\\<begin\\>\$\\|\$\\<module\\>\$" t (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) store-match-data nesting verilog-in-star-comment-p throw comment beginning-of-line "[ 	]*`[ou]vm_" "[ 	]*`vmm_" directive verilog-in-struct-nested-p nested-struct block verilog-in-paren verilog-in-coverage-p 1 cpp verilog-continued-line-1 cexp " 	" constraint statement "\\<else\\>" move 2 verilog-forward-syntactic-ws 3 verilog-beg-of-statement 4 "\$\\<begin\\>\$\\|\$\\<end\\>\$" 5 "\$\\<randcase\\>\\|\\<case[xz]?\\>[^:]\$\\|\$\\<endcase\\>\$" 6 "\$\\<function\\>\$\\|\$\\<endfunction\\>\$" 7 "\$\\<task\\>\$\\|\$\\<endtask\\>\$" 8 "\$\\<specify\\>\$\\|\$\\<endspecify\\>\$" 9 "\$\\<table\\>\$\\|\$\\<endtable\\>\$" 10 "\$\\<generate\\>\$\\|\$\\<endgenerate\\>\$" 11 "\$\\<fork\\>\$\\|\$\\<join\\(_any\\|none\$?\\>\\)" 12 "\$\\<class\\>\$\\|\$\\<endclass\\>\$" 13 "\$\\<covergroup\\>\$\\|\$\\<endgroup\\>\$" REGEXP mdata lim structres verilog-directive-re-1 verilog-indent-lists verilog-in-constraint-re sp verilog-complete-reg verilog-indent-begin-after-if verilog-no-indent-begin-re elsec verilog-ends-re verilog-align-ifelse verilog-property-re nest reg type skip verilog-calc-1 cparenexp #s(hash-table size 5 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (case 735 statement 745 defun 752 constraint 759 nested-struct 765)) verilog-case-indent-level verilog-current-indent-level] 5 (#$ . 158984)])
#@44 Show matching nesting block for debugging.
(defalias 'verilog-wai #[nil "\212\303 \304\204\f�\305\n\203$�\306 \204$�\307 \204$�\310 \203$�\311\202=�\312\267\202:�\313 \202=�i\202=�\314\202=�\315 \316\317	#+\207" [type depth verilog-indent-lists verilog-calc-1 nil cpp verilog-in-coverage-p verilog-in-struct-p verilog-in-paren 1 #s(hash-table size 3 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (case 42 statement 48 defun 53)) verilog-case-indent-level 0 verilog-current-indent-level message "You are at nesting %s depth %d"] 4 (#$ . 162703) nil])
(defalias 'verilog-calc-1 #[nil "\3062\362\307\310Q\311 \n\312\313\3146\315
\f#\203;�\316 \2116\203;�\317 \203;�\3206\f\2037�`\fV\2028�\321\204�\3226!\210\323\225,\203\354\3242\350\312f\325\232\203p�\326 \205\347	\203i�\327\312!\210\330\312w\210\331\306\332\"\202\347\331\306\333\"\202\347\312f\334\232\203\244�\312\335 787\205\240�\336 \323V\203\215�\337u\210\340 \2118\203\236�8b\210\337u\202\240�\341u*\202\347\3429!\203\204\343\225\203\321�`:\344 \210\342;!\203\305�\331\306\345\"\210\202\311�:b\210)\331\306\345\"\202\347\346\225\203\363�`:\344 \210\342<!\203\347�\321\202\357�:b\210\331\306\347\")\202\347\350\225\203 `:\351 \203\321\202\212\344 \210\342=!)\203\321\202:b\210\331\306\347\")\202\347\342\352!\203_\344 \210\342>!\2037\331\324\353\"\202\347\342\354!\204C\342\355!\203J\331\306\333\"\202\347\3429!\203X\331\306\347\"\202\347\331\306\356\"\202\347\342\357!\203}\344 \210\342?!\203v\331\324\333\"\202\347\331\306\347\"\202\347\331\306\347\"\202\347\342@!\203\244\360 \210\361 \205\347\362 \210\342;!\205\347\331\306\345\"\202\347\342A!\203\321\342B!\203\312\363 \204\274\364 \203\303\331\324\353\"\202\347\331\306\356\"\202\347\331\306\356\"\202\347\342C!\203\337\331\306\365\"\202\347o\205\347\331\306\365\"0\210\202\f�\331\306\365\"*0\207" [verilog-indent-re inconstraint re NOERROR BOUND REGEXP nesting "\${\\|}\\|" "\$" verilog-in-coverage-p nil move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0 continue 123 verilog-at-constraint-p beginning-of-line " 	" throw constraint statement 125 verilog-at-close-constraint-p verilog-in-paren-count 1 verilog-parenthesis-depth -1 looking-at 2 verilog-beg-of-statement case 4 block 17 verilog-in-paren "\\<class\\|struct\\|function\\|task\\>" foo "\\<pure\\>\\s-+\\<virtual\\>\\s-+\$?:\\<\\(local\\|protected\\|static\$\\>\\s-+\\)?\\<\$function\\|task\$\\>\\s-+" "\\<typedef\\>\\s-+\$?:\\<virtual\\>\\s-+\$?\\<class\\>\\s-+" defun "\\<property\\>" verilog-leap-to-head verilog-in-case-region-p verilog-leap-to-case-head verilog-in-generate-region-p verilog-in-deferred-immediate-final-p cpp mdata there par-pos verilog-beg-block-re-ordered here verilog-extended-case-re verilog-disable-fork-re verilog-default-clocking-re verilog-dpi-import-export-re verilog-property-re verilog-end-block-re verilog-defun-level-re verilog-defun-level-generate-only-re verilog-cpp-level-re] 5])
#@145 Return indentation level for directive.
For speed, the searcher looks at the last directive, not the indent
of the appropriate enclosing block.
(defalias 'verilog-calculate-indent-directive #[nil "\306\307\212\310 \210	\307W\203\216�\n\311\312\313\314
\f#\203=�\315 \211\203=�\316 \203=�\317\f\2039�`\fV\202:�\312\204�\320!\210\307\225,\203\216�\212\321\311x\210n)\203U�\322 \323!\203j�	\307W\203j�Z\202�\323!\203�	\307Y\203�\\\202�\323!\203�\\\202�\307	\\])\212\310 \210\321\311w\210\323!\204\253�\323!\203\262�\307Z])*\207" [ind base verilog-directive-re NOERROR BOUND REGEXP -1 0 beginning-of-line nil t (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) store-match-data " 	" current-indentation looking-at mdata verilog-directive-end verilog-indent-level-directive verilog-directive-middle verilog-directive-begin] 4 (#$ . 165785)])
(defalias 'verilog-leap-to-case-head #[nil "\306\307U?\205s�\310\311\312\313\314\n	#\2035�\315 \211\2035�\316 \2035�\317\n\2031�`\nV\2022�\320\204�\321\f!\210\307\225,\210\306\225\203Y�`\322 \210\323!\204Q�
b\210)S\211\202�\324\225\203e�T\211\202�o\203�\325\320!\210\307\211\202�)\207" [nest NOERROR BOUND REGEXP mdata here 1 0 "\$\\<randcase\\>\\|\\(\\<unique0?\\s-+\\|priority\\s-+\$?\\<case[xz]?\\>\\)\\|\$\\<endcase\\>\$" nil move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data verilog-beg-of-statement looking-at 3 ding verilog-extended-case-re] 5])
#@114 Move point to the head of this block.
Jump from end to matching begin, from endcase to matching case, and so on.
(defalias 'verilog-leap-to-head #[nil "\306\211\307\310\311\312!\203�\313\202\344�\311\314!\203 �\315\316\202\344�\311\317!\2033�\3012-�\320 0\210\306\202\344�\311\321!\203>�\322\202\344�\311\323!\203I�\324\202\344�\311\325!\203T�\326\202\344�\311\327!\203_�\330\202\344�\311\331!\203l�\332\316\202\344�\311\333!\203w�\334\202\344�\311\335!\203\202�\336\202\344�\311\337!\203\215�\340\202\344�\311\f!\203\236�\341
\342\f\343\260\202\344�\311;!\203\262�\341<\342;\343\260\202\344�\311=!\203\306�\341>\342=\343\260\202\344�\311\344!\203\321�\345\202\344�\311\346!\203\334�\347\202\344�\311\350!\203\344�\351\205\3522	\307=\203\256\306?\306\353@AB\354C\355BA@#\203,\356 \211C\203,\357 \203,\360CA\203(`AV\202)\361\204\362C!\210\363\225,\205\252\310\225\203y\311\364!\203Z`D\365 \210\311E!\204VDb\210S)\202]S\363U\203h\366\352\310\"\210\n\203\365�\nU\203\365�?\211\202\366�\367\225\203\204T\202\365�\370\225\203\227T?\371\211\202\366�\372\225\203\365�T?\322\211\202\366�)\202\306\353@AB\354C\355BA@#\203\345\356 \211C\203\345\357 \203\345\360CA\203\341`AV\202\342\361\204\272\362C!\210\363\225,\203\377\310\225\203\377\365 \210\366\352\310\"\202\366\352\310\"0,\207" [nest nesting snest reg verilog-uvm-end-re verilog-uvm-begin-re nil yes 1 looking-at "\\<end\\>" "\$\\<begin\\>\$\\|\$\\<end\\>\$\\|\$\\<endcase\\>\$\\|\$\\<join\\(_any\\|_none\$?\\>\\)" "\\<endtask\\>" "\$\\<task\\>\$\\|\$\\(\\<\\(virtual\\|protected\\|static\$\\>\\s-+\\)+\\<task\\>\\)" no "\\<endcase\\>" verilog-leap-to-case-head "\\<join\$_any\\|_none\$?\\>" "\$\\<fork\\>\$\\|\$\\<join\\(_any\\|_none\$?\\>\\)" "\\<endclass\\>" "\$\\<class\\>\$\\|\$\\<endclass\\>\$" "\\<endtable\\>" "\$\\<table\\>\$\\|\$\\<endtable\\>\$" "\\<endspecify\\>" "\$\\<specify\\>\$\\|\$\\<endspecify\\>\$" "\\<endfunction\\>" "\$\\<function\\>\$\\|\$\\(\\<\\(virtual\\|protected\\|static\$\\>\\s-+\\)+\\<function\\>\\)" "\\<endgenerate\\>" "\$\\<generate\\>\$\\|\$\\<endgenerate\\>\$" "\\<endgroup\\>" "\$\\<covergroup\\>\$\\|\$\\<endgroup\\>\$" "\\<endproperty\\>" "\$\\<property\\>\$\\|\$\\<endproperty\\>\$" "\$" "\\|" "\$" "\\<endinterface\\>" "\$\\<interface\\>\$\\|\$\\<endinterface\\>\$" "\\<endsequence\\>" "\$\\<\\(rand\$?sequence\\>\\)\\|\$\\<endsequence\\>\$" "\\<endclocking\\>" "\$\\<clocking\$\\|\$\\<endclocking\\>\$" skip move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0 "fork" verilog-beg-of-statement throw 2 3 "\$\\<randcase\\>\\|\\<case[xz]?\\>[^:]\$\\|\$\\<endcase\\>\$" 4 verilog-ovm-end-re verilog-ovm-begin-re verilog-vmm-end-re verilog-vmm-begin-re sreg NOERROR BOUND REGEXP mdata here verilog-disable-fork-re] 6 (#$ . 167363)])
#@74 Return true if this is a continued line.
Set point to where line starts.
(defalias 'verilog-continued-line #[nil "\301\302y\303=\2030�\304\210\305 \210o\203�\304\2022�\2032�\212\306\304x\210n)\2042�\307 \211\204�\2022�\304)\207" [continued t -1 0 nil verilog-backward-ws&directives " 	" verilog-backward-token] 3 (#$ . 170335)])
#@66 Step backward token, returning true if this is a continued line.
(defalias 'verilog-backward-token #[nil "\306 \210n\203	�\307\207h\310U\203�\307\207h\311U\203�\312u\210\313 ?\207h\314U\203+�\312u\210\315 ?\207h\316U\2039�\312u\210\317 \210\307\207h\320U\203G�\312u\210\321 \210\322\207h\323U\203\370�\312u\210\324\325!\210\306 \210`\326\312!\210\327\330!\203j�\327\331!?\202\366�\327	!\203t�\307\202\366�\327\n!\203~�\322\202\366�\327!\203\210�\322\202\366�\327\f!\203\222�\307\202\366�\327
!\203\234�\322\202\366�\327%!\203\247�\322\202\366�\327&!\203\262�\307\202\366�\327'!\203\275�\322\202\366�\327(!\203\310�\307\202\366�\327\332!\203\322�\307\202\366�b\210h\333U\203\352�\312u\210\212\334 \210\327\335!)?\202\366�h\336U\203\365�\312u\202\366�\322)\207\326\312!\210h\337U\204h\333U\204h\340U\203\326\312!\210\202\374�\327\341!\203\322\207\327)!\203&\322\207\327*!\203/\307\207`\306 \210h\342U\203O\312u\210\306 \210\343 \210\327+!?\205m\322\202mh\336U\203\\\312u\210\322\202mh\344U\203i\312u\210\322\202mb\210\322)\207" [back verilog-uvm-statement-re verilog-uvm-begin-re verilog-uvm-end-re verilog-ovm-statement-re verilog-ovm-begin-re verilog-backward-syntactic-ws nil 59 125 -1 verilog-at-close-constraint-p 123 verilog-at-constraint-p 34 verilog-skip-backward-comment-or-string 93 verilog-backward-open-bracket t 41 verilog-backward-up-list 1 forward-word-strictly looking-at "\\<\$always\\(_latch\\|_ff\\|_comb\$?\\|case\$\\|[xz]\$\\|for\$\\|each\\|ever\$\\|i\$f\\|nitial\$\\|repeat\\|while\\)\\>" "\\<randcase\\>\\|\\<case[xz]?\\>[^:]" "\\<`" 64 verilog-backward-token "\\<\$always\\(_latch\\|_ff\\|_comb\$?\\|initial\\|while\\)\\>" 35 95 46 "\\<else\\>" 58 backward-sexp 96 verilog-ovm-end-re verilog-vmm-statement-re verilog-vmm-begin-re verilog-vmm-end-re verilog-behavioral-block-beg-re verilog-indent-re verilog-nameable-item-re] 2 (#$ . 170679) nil])
#@70 Move backwards putting point after first non-whitespace non-comment.
(defalias 'verilog-backward-syntactic-ws #[nil "\300 \210\301\302 [!\207" [verilog-skip-backward-comments forward-comment buffer-size] 2 (#$ . 172595)])
#@71 As with `verilog-backward-syntactic-ws' but use `verilog-scan' cache.
(defalias 'verilog-backward-syntactic-ws-quick #[nil "o\203�\300\207\301\302!\303W\204��h\304=\203�\305u\210\202��\306`S!\204'�\306`!\2050�\307\310\300\311#\210\202��\207" [nil skip-syntax-backward " " 0 10 -1 verilog-inside-comment-or-string-p re-search-backward "[/\"]" t] 4 (#$ . 172823)])
(defalias 'verilog-forward-syntactic-ws #[nil "\300 \210\301\302 !\207" [verilog-skip-forward-comment-p forward-comment buffer-size] 2])
#@109 Backward skip over syntactic whitespace and compiler directives for Emacs 19.
Optional BOUND limits search.
(defalias 'verilog-backward-ws&directives #[(&optional bound) "\214\206�e\211\306`W\205\346�\212\307 )\3108\203]�\311\306\312\313\314
\f#\203M�\315 \211\203M�\316 \203M�\317
\203I�`
V\202J�\320\204&�\321!\210\322\225,\210\323\306x\210\202\235�\3248\203\235�\325\306\312\313\314
\f#\203\224�\315 \211\203\224�\316 \203\224�\317
\203\220�`
V\202\221�\320\204m�\321!\210\322\225,\210)`}\210	`U?\205\346�`\326 \210\212\327 \210\330\331\306\"\203\276�\332y\204\262� \203\316�\333 \203\316�\334e!\202\332�\335!!\203\331�`\202\332�\306)\211\203\242�\nb\210\202\242�,\207" [bound here p state NOERROR BOUND nil verilog-syntax-ppss 7 "//" move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0 "/" 4 "/\\*" verilog-skip-backward-comments beginning-of-line verilog-looking-back "\\\\[\n
\f]" -1 verilog-within-translate-off verilog-back-to-start-translate-off looking-at REGEXP mdata verilog-highlight-translate-off verilog-directive-re-1] 5 (#$ . 173332)])
#@108 Forward skip over syntactic whitespace and compiler directives for Emacs 19.
Optional BOUND limits search.
(defalias 'verilog-forward-ws&directives #[(&optional bound) "\214\206�d\211\306`V\205\241�\212\307 )\3108\203)�\306\210\311u\210\312\306w\210\202i�\3138\203i�\314\306\315\316\317
\f#\203`�\320 \211\203`�\321 \203`�\322
\203\\�`
W\202]�\323\2049�\324!\210\325\225,\210)`}\210	`U?\205\241�`\306\326\327 !\210\330\331!\203\210�\325\225b\210\212\332 \210\330!\203\225�\323)\n\203n�\332\333!\210\202n�,\207" [bound here jump state NOERROR BOUND nil verilog-syntax-ppss 7 1 " 	\n\f" 4 "\\*/\\s-*" move (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) t store-match-data 0 forward-comment buffer-size looking-at "\\s-*(\\*.*\\*)\\s-*" beginning-of-line 2 REGEXP mdata verilog-directive-re-1] 5 (#$ . 174498)])
#@41 Return true if in a star or // comment.
(defalias 'verilog-in-comment-p #[nil "\212\301 )\3028\206�\3038)\207" [state verilog-syntax-ppss 4 7] 2 (#$ . 175384)])
#@35 Return true if in a star comment.
(defalias 'verilog-in-star-comment-p #[nil "\212\301 )\3028\205�\3038?)\207" [state verilog-syntax-ppss 4 7] 2 (#$ . 175555)])
#@36 Return true if in a slash comment.
(defalias 'verilog-in-slash-comment-p #[nil "\212\301 )\3028)\207" [state verilog-syntax-ppss 7] 2 (#$ . 175726)])
#@40 Return true if in a string or comment.
(defalias 'verilog-in-comment-or-string-p #[nil "\212\301 )\3028\206�\3038\206�\3048)\207" [state verilog-syntax-ppss 3 4 7] 2 (#$ . 175884)])
#@61 Return true if point is in an attribute (* [] attribute *).
(defalias 'verilog-in-attribute-p #[nil "\305 \306\216\212\307\310\311\312\313\n	#\2032�\305 \211\2032�\314 \2032�\315\n\203.�`\nV\202/�\316\204�\317\f!\210\320\225,\210\321\225\203K�\321\225b\210\322\323!\210\310\202]�\324\225\203\\�\324\224b\210\322\325!\210\310\202]�\310+\207" [save-match-data-internal NOERROR BOUND REGEXP mdata match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] "\$(\\*\$\\|\$\\*)\$" nil move (nil nil) re-search-backward verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0 1 looking-at "\\s-*)" 2 "(\\s-*"] 4 (#$ . 176078)])
#@67 Return true if point is in a parameter assignment #( p1=1, p2=5).
(defalias 'verilog-in-parameter-p #[nil "\305 \306\216\212\307\310\311\312\313\n	#\2032�\305 \211\2032�\314 \2032�\315\n\203.�`\nV\202/�\316\204�\317\f!\210\320\225,\210\321\224+\247\207" [save-match-data-internal NOERROR BOUND REGEXP mdata match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] "\$#(\$\\|\$)\$" nil move (nil nil) re-search-backward verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0 1] 4 (#$ . 176764)])
#@36 Return true if in an escaped name.
(defalias 'verilog-in-escaped-name-p #[nil "\212\300u\210\301\302x\210`f\303\232\205�\304)\207" [-1 "^ 	\n\f" nil 92 t] 2 (#$ . 177327)])
#@32 Return true if in a directive.
(defalias 'verilog-in-directive-p #[nil "\212\301 \210\302!)\207" [verilog-directive-re-1 beginning-of-line looking-at] 2 (#$ . 177507)])
#@58 Return true if in a ( ) expression (but not { } or [ ]).
(defalias 'verilog-in-parenthesis-p #[nil "\305 \306\216\212\307\310\311\312\313\n	#\2032�\305 \211\2032�\314 \2032�\315\n\203.�`\nV\202/�\316\204�\317\f!\210\320\225,\210\321\224+\247\207" [save-match-data-internal NOERROR BOUND REGEXP mdata match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] "\$(\$\\|\$)\$" nil move (nil nil) re-search-backward verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0 1] 4 (#$ . 177683)])
#@93 Return true if in a parenthetical expression.
May cache result using `verilog-syntax-ppss'.
(defalias 'verilog-in-paren #[nil "\212\301 )\211@\302V)\207" [state verilog-syntax-ppss 0] 3 (#$ . 178238)])
#@79 Return paren depth, floor to 0.
May cache result using `verilog-syntax-ppss'.
(defalias 'verilog-in-paren-count #[nil "\212\301 )\211@\302V\203�@\202�\302)\207" [state verilog-syntax-ppss 0] 3 (#$ . 178447)])
#@117 Return true if in a parenthetical expression.
Always starts from `point-min', to allow inserts with hooks disabled.
(defalias 'verilog-in-paren-quick #[nil "\212\301e`\")\211@\302V)\207" [state parse-partial-sexp 0] 4 (#$ . 178667)])
#@41 Return true if in a struct declaration.
(defalias 'verilog-in-struct-p #[nil "\212\300 \205\f�\301\302!\210\303 )\207" [verilog-in-paren verilog-backward-up-list 1 verilog-at-struct-p] 2 (#$ . 178908) nil])
#@95 Return nil for not in struct.
Return 0 for in non-nested struct.
Return >0 for nested struct.
(defalias 'verilog-in-struct-nested-p #[nil "\301\212\302 \205�\303\304!\210\305 \211\205�\306 \203�i\202�\307*\207" [col nil verilog-in-paren verilog-backward-up-list 1 verilog-at-struct-mv-p verilog-in-struct-p 0] 3 (#$ . 179121) nil])
#@58 Return true if in a constraint or coverpoint expression.
(defalias 'verilog-in-coverage-p #[nil "\212\300 \205\f�\301\302!\210\303 )\207" [verilog-in-paren verilog-backward-up-list 1 verilog-at-constraint-p] 2 (#$ . 179465) nil])
#@66 If at the } that closes a constraint or covergroup, return true.
(defalias 'verilog-at-close-constraint-p #[nil "\300f\301\232\205*�\302 \205*�\212\303 \210`Sf\304\232\204(�`Sf\301\232\204(�`Sf\305\232\205)�`)\207" [nil 125 verilog-in-coverage-p verilog-backward-ws&directives 59 123] 2 (#$ . 179701)])
#@96 If at the { of a constraint or coverpoint definition, return true, moving point to constraint.
(defalias 'verilog-at-constraint-p #[nil "\212`\305f\306\232\205A�\3071�\310 0\202�\210\305\202A�\205A�\311u\210\312 \210`Sf\306\232\204:�`Sf\313\232\204:�`Sf\314\232\205A�\315\316`{\"?*\205\234�`\317\312 \210\320 \210\321\322P!\203q�\323\321\324!\203k�\312 \210\325 \210\326 \210\202\215�\327 \210\202\215�\321\330!\203\215�\327 \210\315\f\n`{\"\204\215�\321\331P!\203\215�\323	\317=\203\232�\nb\210\305\202\233�\323*\207" [p pass pt verilog-in-constraint-re verilog-named-block-re nil 123 (error) forward-list -1 verilog-backward-ws&directives 59 125 string-match "^{\\s-*[0-9a-zA-Z_]+\\s-*{" 0 verilog-backward-token looking-at "\\<constraint\\|coverpoint\\|cross\\|with\\>\\|" 1 "\\<with\\>" beginning-of-line verilog-forward-ws&directives verilog-beg-of-statement "\\<\\w+\\>\\|\\s-*(\\s-*\\S-+" "\\<\$constraint\\|\\(?:\\w+\\s-*:\\s-*\$?\$coverpoint\\|cross\$\\|with\\)\\>\\|"] 4 (#$ . 180010)])
#@57 If at the { of a struct, return true, not moving point.
(defalias 'verilog-at-struct-p #[nil "\212\300f\301\232\205�\302 \205�\303\304!)\207" [nil 123 verilog-backward-token looking-at "\\<struct\\|union\\|packed\\|\$un\$?signed\\>"] 2 (#$ . 181027)])
#@63 If at the { of a struct, return true, moving point to struct.
(defalias 'verilog-at-struct-mv-p #[nil "`\301f\302\232\203\"�\303 \203\"�\304\305!\203�\306 \210`\202&�b\210\301\202&�b\210\301)\207" [pt nil 123 verilog-backward-token looking-at "\\<struct\\|union\\|packed\\|\$un\$?signed\\>" verilog-beg-of-statement] 2 (#$ . 181289)])
#@48 If at the } that closes a struct, return true.
(defalias 'verilog-at-close-struct-p #[nil "\300f\301\232\205�\302 \205�\212\303\304!\205�\305)\207" [nil 125 verilog-in-struct-p looking-at "}\$?:\\s-*\\w+\\s-*\$?;" 1] 2 (#$ . 181636)])
#@49 Return non zero if in parenthetical-expression.
(defalias 'verilog-parenthesis-depth #[nil "\212\300 A@)\207" [verilog-syntax-ppss] 1 (#$ . 181882)])
#@40 Return true if in a string or comment.
(defalias 'verilog-skip-forward-comment-or-string #[nil "\212\301 )\3028\203�\303\304!\210\305\202-�\3068\203 �\307y\210\305\202-�\3108\203,�\303\311!\202-�\312)\207" [state verilog-syntax-ppss 3 search-forward "\"" t 7 1 4 "*/" nil] 2 (#$ . 182038)])
#@40 Return true if in a string or comment.
(defalias 'verilog-skip-backward-comment-or-string #[nil "\212\301 )\3028\203�\303\304!\210\305\2024�\3068\203%�\303\307!\210\310\311x\210\305\2024�\3128\2033�\303\313!\210\305\2024�\311)\207" [state verilog-syntax-ppss 3 search-backward "\"" t 7 "//" "/" nil 4 "/*"] 2 (#$ . 182340)])
#@39 Return true if a comment was skipped.
(defalias 'verilog-skip-backward-comments #[nil "\302\212\303 )\304	8\203�\305\306!\210\307\310x\210\311\310x\210\302\202\225�\312	8\203/�\305\313!\210\311\310x\210\302\202\225�o\204Q�`Sf\314U\203Q�`S\206A�`Sf\315U\203Q�`\316Zb\210\302\202\225�o\204\217�`Sf\317U\203\217�`S\206c�`Sf\315U\203\217�\320\321\310\"\204\217�`\316Zb\210\305\322\310\302#\203\206�\311\310x\210\302\202\225�`\316\\b\210\310\202\225�\311\310x\323U?)\211\204�)\310\207" [more state t verilog-syntax-ppss 7 search-backward "//" "/" nil " 	\n\f" 4 "/*" 47 42 2 41 verilog-looking-back "(\\s-*\\*)" "(*" 0] 5 (#$ . 182676)])
#@45 If in comment, move to end and return true.
(defalias 'verilog-skip-forward-comment-p #[nil "\303\212\304 )\305	8\203�\306\202?�\307	8\203!�\303\210\310u\210\306\202?�\311	8\203/�\312\313!\210\306\202?�\314 \203>�\312\315\303\306#\210\306\202?�\303\316\303w\210\317\320!\203h�`\321\225b\210\312\313\303\306#\203b�\316\303w\210\306\211\202\223�b\210\202\226�\317\322!\203\222�\317\323!\204\222�`\321\225b\210\312\315\303\306#\203\214�\316\303w\210\306\211\202\223�b\210\202\226�\303\204D�\n+\207" [h state skip nil verilog-syntax-ppss 3 t 7 1 4 search-forward "*/" verilog-in-attribute-p "*)" " 	\n\f" looking-at "/\\*" 0 "(\\*" "(\\*\\s-*)"] 4 (#$ . 183320)])
#@83 Cheap version of indent line.
Only look at a few lines to determine indent level.
(defalias 'verilog-indent-line-relative #[nil "\303`\304\305!\203F�o\203�\306\307D\202M�\310 \203;�`\310 \203,�b\210\311\312 D\2024�\nb\210\313\312 D)b\210\202M�b\203M�\314 \202M�\315\303w\210\314 \316	!*\207" [sp indent-str sp1 nil looking-at "^[ 	]*$" cpp 0 verilog-continued-line statement verilog-current-indent-level block verilog-calculate-indent " 	" verilog-do-indent] 2 (#$ . 183997) nil])
#@34 Indent for special part of code.
(defalias 'verilog-indent-line #[nil "\300\301 !\207" [verilog-do-indent verilog-calculate-indent] 2 (#$ . 184496)])
(defalias 'verilog-do-indent #[(indent-str) "@A@\211\306\267\202f`\307 \210h\310U\204#�\212\311 \210\312\f!)\203\215�\313\212\314u\210\311 \210`\312\f!\203j�\315\225b\210\316\313w\2104\203U�g\317U\203U�\320u\210\321\320!\210\316\313w\210\202f�g\322U\203f�\320u\210\323\314!\210\316\313w\210i\202q�
b\210i5\\)6b\210\3246!\2107\204\211�\325 \203\211�\326 \210*\202#h\327U\203\251�b\210\330\331\n8\"A!6\3246!\210)\202#b\210\3136\311 \210`W\203\332\3339:;\334<\335;:9#\203\357�\336 \211<\203\357�\337 \203\357�\340<:\203\353�`:W\202\354�\341\204\304�\342<!\210\315\225,\203\343\344`\345Z`T{\206\346\"\204i6\202\330\331\n8\"A!6b\210\3246!\210))\202\313\212\323\320!\210\320u\2107\203=\316\313w\210\202@\347 \210`i)6\212b\210\347 \210`\312\f!)=\3246!\210=\203b\326 \210+\202\312>!\204w\350 \204w\351 \203\220\n\352=\203\204	?Z\202\205	6\3246!\210)\202\n\353=\203\274\312\354!\204\274\312\355!\203\251\324	!\210\202\330\331\n8\"A!6\3246!\210)\202\n\356=\203\320\312@!\203\320\324\315!\210\202\n\356=\204\334\n\357=\203\361\312\f!\203\361\312\f\360P!\204\361\361	!\210\202\312\362!\204\330\331\n8\"A!6\3246!\210)\312\363!\203\316\313w\210*\207" [indent-str ind type here verilog-declaration-re fst #s(hash-table size 2 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (cexp 13 cparenexp 295)) verilog-backward-syntactic-ws 44 verilog-beg-of-statement-1 looking-at nil -1 0 " 	" 96 1 forward-word-strictly 91 verilog-backward-up-list indent-line-to verilog-in-paren verilog-pretty-declarations-auto 41 eval assoc "=[ 	]*" move (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) t store-match-data string-match "\\[=.\\|#=#\\||=>" 2 "" verilog-forward-syntactic-ws verilog-at-close-constraint-p verilog-at-close-struct-p statement case "^[ 	]*$" "\\<endcase\\>" defun block "\\s-+\$function\\|task\\|class\$\\b" verilog-indent-declaration "\f" "[ 	]+$" verilog-indent-declaration-macros verilog-cexp-indent val verilog-indent-lists verilog-indent-alist NOERROR BOUND REGEXP mdata decl verilog-end-block-re verilog-indent-level verilog-zero-indent-re] 5])
#@51 Return the indent-level of the current statement.
(defalias 'verilog-current-indent-level #[nil "\212\301\302 \210\303 \211\203�b\210\302 \210\303 \211\204
�\304\301w\210i*\207" [par-pos nil beginning-of-line verilog-parenthesis-depth " 	"] 3 (#$ . 186858)])
#@97 Return the indent-level of the current statement.
Do not count named blocks or case-statements.
(defalias 'verilog-case-indent-level #[nil "\212\306\307w\210\310!\203�i\202X�\310	!\204W�\310\311!\203W�\312\307\313\314\315\f\n#\203G�\316 \211\203G�\317 \203G�\320\203C�`W\202D�\313\204#�\321
!\210\322\225,\210\306\307w\210i\202X�i)\207" [verilog-named-block-re verilog-extended-case-re NOERROR BOUND REGEXP mdata " 	" nil looking-at "^[^:;]+[ 	]*:" ":" t (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) store-match-data 0] 4 (#$ . 187128)])
#@33 Indent current line as comment.
(defalias 'verilog-indent-comment #[nil "\302 \203�\212\303\304\305\306#\210iT)\202#�\203�\202#�\212\303\307\305\306#\210i)\310	!\210	)\207" [comment-column stcol verilog-in-star-comment-p re-search-backward "/\\*" nil t "//" indent-line-to] 4 (#$ . 187726)])
#@44 Make more comment lines like the previous.
(defalias 'verilog-more-comment #[nil "\303\304 \203�\212\305\306\307\310\311#\210iT)\202'�	\203�	\202'�\212\306\312\310\311#\210i)\211j\210\205@�\212\313y\210\314\310w\210\315\316!)\205@�\317c*\207" [star comment-column stcol 0 verilog-in-star-comment-p 1 re-search-backward "/\\*" nil t "//" -1 " 	" looking-at "\\*" "* "] 5 (#$ . 188029)])
#@120 Return the column number the line should be indented to.
_ARG is ignored, for `comment-indent-function' compatibility.
(defalias 'verilog-comment-indent #[(&optional _arg) "\301 \203�\212\302\303\304\305#\210iT)\207\203�\207\212\302\306\304\305#\210i)\207" [comment-column verilog-in-star-comment-p re-search-backward "/\\*" nil t "//"] 4 (#$ . 188428)])
#@74 Call `verilog-pretty-declarations' QUIET based on `verilog-auto-lineup'.
(defalias 'verilog-pretty-declarations-auto #[(&optional quiet) "\302=\204\f�\303=\205�\304	!\207" [verilog-auto-lineup quiet all declarations verilog-pretty-declarations] 2 (#$ . 188793)])
#@89 Line up declarations around point.
Be verbose about progress unless optional QUIET set.
(defalias 'verilog-pretty-declarations #[(&optional quiet) "\306 `\307\211`\307\211-\307\211./\307\21101\212\310 \210\311 \210\312 ?\205\322\3132!\205\322\314 \203\301�\315\316!	b\210\315\317!\210\307y\2102\n\320345\3216\322543#\203{�\323 \2116\203{�\324 \203{�\32564\203w�`4W\202x�\326\204P�\3276!\210\330\225,\210\330\224b\210\331\307x\210`-\306 -\307\223.-b\210\315\316!\210\316u\210\332 \210`/\306 /\307\2230-b\210\317u\210\331\307w\210i1\202&\333 \210\3132!\203\344�o\204\344�\331\307x\210`\310 \210\332 \210\316u\210\333 \210\202\304�	-\306 -\307\223.\fb\210\334 \210`\311 \210\3132!\203\f\334 \210`\311 \210\202\372�	/\306 /\307\2230-b\210\335\336 !\210\337 \210i1\340.!b\2107\204?/-Z\341V\203?\342\343!\210\3400!`	W\203\356\212\331\307x\210n)\203\250\337 \210\3441!\210\337 \210`	W\203?\345	\320345\3216\322543#\203\234\323 \2116\203\234\324 \203\234\32564\203\230`4W\202\231\326\204q\3276!\210\330\225,\210\202?\346 \210\345	\320345\3216\322543#\203\342\323 \2116\203\342\324 \203\342\32564\203\336`4W\202\337\326\204\267\3276!\210\330\225,\210\202?\347\340.!0\"\340.!b\210\3400!\211`Z\211\330V\203\311`7\204\342\350\"\210\337 \2108\203'\3139!\204.\313:!\203\231\330\225;;\307\223\210\351;\320345\3216\322543#\203p\323 \2116\203p\324 \203p\32564\203l`4W\202m\326\204E\3276!\210\330\225,\203\217\316u\210\346 \210\340!b\210\346 \210
j\210\202\225\346 \210
j\210)\202\303\352\340.!!\203\254	b\210\344
!\210\202\303\353 \203\272	b\210\334 \210\202\303	b\210\337 \210\316y\210\317y\210\202\3757?\205\322\342\354!.\f\207" [m1 e el r here ind make-marker nil beginning-of-line verilog-forward-syntactic-ws verilog-in-directive-p looking-at verilog-parenthesis-depth verilog-backward-up-list -1 1 move (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) t store-match-data 0 " 	" verilog-backward-syntactic-ws verilog-beg-of-statement-1 verilog-end-of-statement verilog-do-indent verilog-calculate-indent verilog-forward-ws&directives marker-position 100 message "Lining up declarations..(please stand by)" indent-line-to "[ 	\n\f]" just-one-space verilog-get-lineup-indent "%d" "[[#`]" verilog-continued-line-1 verilog-in-struct-p "" start startpos end endpos base-ind verilog-declaration-re NOERROR BOUND REGEXP mdata quiet verilog-indent-declaration-macros verilog-declaration-re-2-macro verilog-declaration-re-2-no-macro p] 5 (#$ . 189065) nil])
#@111 Line up expressions around point.
If QUIET is non-nil, do not print messages showing the progress of line-up.
(defalias 'verilog-pretty-expr #[(&optional quiet) "\306 ?\205m\212\307P\307	P\310 \210\311!?\205l\311\f!\205l\212\312\225b\210\313 ?\2053�\314 ?\2053�\306 ?)\205l\212\310 \210`\315 \210\310 \210\311\n!\204^�\311\f!\203^�o\204^�`\315 \210\310 \210\202C�
*&\212\316\210`\317 \210\310 \210\311\n!\204\216�\311\f!\203\216�\316\210
`=\204\216�`\317 \210\310 \210\202n�
*'\320\321\322&'\"\"(\323 '\316\223)&b\210\324\325 !\210*\204\301�'&Z\326V\203\301�\327\330!\210`\331)!W\203\341�\310 \210\212\332\f!\210)\324\325 !\210\316\210\317 \210\202\301�\333\f&\331)!#\316+,&b\210\331)!\211+`V\203a*\204\f\327\334+`Z\"\210`+\311\f!\203>\312\224b\210\335 \204[\336 \204[(\2037\316f\337=\2037,Tj\210\202[,j\210\202[\340&!\203Q+b\210\341,!\210\202[+b\210\342 \210\343y\210\344y\210\202\363�*?\205j\327\345!.+\207" [verilog-complete-reg verilog-basic-complete-re regexp1 regexp verilog-assignment-operation-re pt verilog-in-comment-or-string-p "^\\s-*" beginning-of-line looking-at 2 verilog-in-attribute-p verilog-in-parameter-p verilog-backward-syntactic-ws nil verilog-forward-syntactic-ws string-match "<=" buffer-substring-no-properties make-marker verilog-do-indent verilog-calculate-indent 100 message "Lining up expressions.. (please stand by)" marker-position verilog-just-one-space verilog-get-lineup-indent-2 " verilog-pretty-expr: %d" verilog-in-parenthesis-p verilog-in-coverage-p 61 verilog-continued-line-1 indent-line-to verilog-forward-ws&directives -1 1 "" start end contains-2-char-operator endmark quiet e ind] 6 (#$ . 191703) nil])
#@53 Remove extra spaces around regular expression MYRE.
(defalias 'verilog-just-one-space #[(myre) "\304!?\205�\304	!\205�\305\225\306\225\nb\210\307 \210b\210\307 *\207" [verilog-complete-reg myre p2 p1 looking-at 1 2 just-one-space] 2 (#$ . 193415) nil])
#@159 Indent current lines as declaration.
Line up the variable names based on previous declaration's indentation.
BASEIND is the base indent to offset everything.
(defalias 'verilog-indent-declaration #[(baseind) "\306 \212\307\310\311\312\313\n	#\203/�\314 \211\203/�\315 \203/�\316	\203+�`	V\202,�\317\204�\320!\210\321\225,\210`)\310\211\322 $%&'\323\324\325(\"A!\\\326
!\210)\327=\204c�)\330=\203\244*\203m�+\206o�,%\317\312\313\n	#\203\233�\314 \211\203\233�\315 \203\233�\316	\203\227�`	V\202\230�\317\204w�\320!\210\321\225,\203\244\321\225b\210\331\310w\210i$&b\210'\323\324\325(\"A!\\\326
!\210*\2038\332-!\2038\321\225.\f.\310\223\210\333.\311\334\335\n	#\203\314 \211\203\336 \203\337	\203`	W\202\317\204\343�\320!\210\321\225,\203&\340u\210\341 \210\342\f!b\210\341 \210$j\210\2024i$U\2044\341 \210$j\210)\202\244\332/!\203\244\321\225.\f.\310\223\210\343.\311\334\335\n	#\203v\314 \211\203v\336 \203v\337	\203r`	W\202s\317\204R\320!\210\321\225,\203\225\340u\210\341 \210\342\f!b\210\341 \210$j\210\202\243i$U\204\243\341 \210$j\210)&b-\207" [NOERROR BOUND REGEXP mdata m1 val point-marker "\$\\<begin\\>\$\\|\$\\<module\\>\$\\|\$\\<task\\>\$" nil move (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) t store-match-data 0 make-marker eval assoc declaration indent-line-to all declarations " 	" looking-at "[[#`]" (nil nil) re-search-forward verilog-skip-forward-comment-or-string (nil nil) -1 just-one-space marker-position "[[`#]" ind lim pos baseind verilog-indent-alist verilog-auto-lineup verilog-indent-declaration-macros verilog-declaration-re-1-macro verilog-declaration-re-1-no-macro verilog-declaration-re-2-macro p verilog-declaration-re-2-no-macro] 5 (#$ . 193681) nil])
#@110 Return the indent level that will line up several lines within the region.
Region is defined by B and EDPOS.
(defalias 'verilog-get-lineup-indent #[(b edpos) "\212\306\307\nb\210\310!`W\203s�\f\203�
\206�\311\312\313#\203R�\314 \211\203R�\315 \203R�\316\203N�`W\202O�\317\204'�\320!\210\306\225,\203�\306\225b\210\321 \210i	V\203l�i\306\225b\210\202�	\306V\203~�	T\202\211�\nb\210\307\210\321 \210iT+\207" [e ind b edpos verilog-indent-declaration-macros verilog-declaration-re-1-macro 0 nil marker-position move (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) t store-match-data verilog-backward-syntactic-ws verilog-declaration-re-1-no-macro NOERROR BOUND REGEXP mdata] 4 (#$ . 195522)])
#@147 Return the indent level that will line up several lines.
The lineup string is searched using REGEXP within the region between points
BEG and END.
(defalias 'verilog-get-lineup-indent-2 #[(regexp beg end) "\212\306	b\210`\nW\203c�\n\307\310\311
\f#\203=�\312 \211\203=�\313 \203=�\314
\2039�`
W\202:�\315\204�\316!\210\306\225,\203�\317 \204�\320\224b\210\321 \210iV\203\\�i\306\225b\210\202�\306V\203n�T\202z�	b\210\322\210\323\322x\210iT\211*\207" [ind beg end regexp NOERROR BOUND 0 move (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) t store-match-data verilog-in-attribute-p 2 verilog-backward-syntactic-ws nil " 	" REGEXP mdata] 5 (#$ . 196297)])
#@73 A useful mode debugging aide.  TYPE and VAL are comments for insertion.
(defalias 'verilog-comment-depth #[(type val) "\212\303 \210\304 \305\210\306\307\310#\203�\311\312!\210\305\210\202\"�\305\210\313c\210)\314u\210\315\316	\n#c)\207" [b type val beginning-of-line point-marker nil re-search-backward " /\\* [#-]# [a-zA-Z]+ [0-9]+ ## \\*/" t replace-match " /* -#  ## */" " /* ##  ## */" -6 format "%s %d"] 4 (#$ . 197022)])
(defvar verilog-str nil)
(defvar verilog-all nil)
(defvar verilog-pred nil)
(defvar verilog-buffer-to-use nil)
(defvar verilog-flag nil)
#@279 True means \<verilog-mode-map>\[verilog-complete-word] should try all possible completions one by one.
Repeated use of \[verilog-complete-word] will show you all of them.
Normally, when there is more than one possible completion,
it displays a list of all possible completions.
(defvar verilog-toggle-completions nil (#$ . 197600))
(byte-code "\300\301!\203\f�\302\303\301\304#\210\300\207" [boundp completion-cycle-threshold make-obsolete-variable verilog-toggle-completions "26.1"] 4)
#@102 Keywords for types used when completing a word in a declaration or parmlist.
(integer, real, reg...)
(defvar verilog-type-keywords '("and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input" "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0" "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pulldown" "pullup" "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor") (#$ . 198094))
#@240 Keywords to complete when at first word of a line in declarative scope.
(initial, always, begin, assign...)
The procedures and variables defined within the Verilog program
will be completed at runtime and should not be added to this list.
(defvar verilog-cpp-keywords '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else" "endif") (#$ . 198671))
#@240 Keywords to complete when at first word of a line in declarative scope.
(initial, always, begin, assign...)
The procedures and variables defined within the Verilog program
will be completed at runtime and should not be added to this list.
(defvar verilog-defun-keywords (append '("always" "always_comb" "always_ff" "always_latch" "assign" "begin" "end" "generate" "endgenerate" "module" "endmodule" "specify" "endspecify" "function" "endfunction" "initial" "final" "task" "endtask" "primitive" "endprimitive") verilog-type-keywords) (#$ . 199052))
#@241 Keywords to complete when at first word of a line in behavioral scope.
(begin, if, then, else, for, fork...)
The procedures and variables defined within the Verilog program
will be completed at runtime and should not be added to this list.
(defvar verilog-block-keywords '("begin" "break" "case" "continue" "else" "end" "endfunction" "endgenerate" "endinterface" "endpackage" "endspecify" "endtask" "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return" "while") (#$ . 199607))
#@241 Keywords to complete when at first word of a line in a task or function.
(begin, if, then, else, for, fork.)
The procedures and variables defined within the Verilog program
will be completed at runtime and should not be added to this list.
(defvar verilog-tf-keywords '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat") (#$ . 200103))
#@235 Keywords to complete when at first word of a line in case scope.
(begin, if, then, else, for, fork...)
The procedures and variables defined within the Verilog program
will be completed at runtime and should not be added to this list.
(defvar verilog-case-keywords '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat") (#$ . 200521))
#@228 Keywords to complete when NOT standing at the first word of a statement.
(else, then, begin...)
Variables and function names defined within the Verilog program
will be completed at runtime and should not be added to this list.
(defvar verilog-separator-keywords '("else" "then" "begin") (#$ . 200905))
#@71 Map of direction for each positional argument to each gate primitive.
(defvar verilog-gate-ios '(("and" "output") ("buf" "output") ("bufif0" "output") ("bufif1" "output") ("cmos" "output") ("nand" "output") ("nmos" "output") ("nor" "output") ("not" "output") ("notif0" "output") ("notif1" "output") ("or" "output") ("pmos" "output") ("pulldown" "output") ("pullup" "output") ("rcmos" "output") ("rnmos" "output") ("rpmos" "output") ("rtran" "inout" "inout") ("rtranif0" "inout" "inout") ("rtranif1" "inout" "inout") ("tran" "inout" "inout") ("tranif0" "inout" "inout") ("tranif1" "inout" "inout") ("xnor" "output") ("xor" "output")) (#$ . 201213))
#@31 Keywords for gate primitives.
(defvar verilog-gate-keywords (mapcar 'car verilog-gate-ios) (#$ . 201867))
#@59 Return index of first letter where STR1 and STR2 differs.
(defalias 'verilog-string-diff #[(str1 str2) "\30321�\304\211T	GV\204�T\nGV\203�\305\303\"\210	H\nH\232\204*�\305\303\"\210T\211\202�\207" [diff str1 str2 done 0 throw] 4 (#$ . 201979)])
#@120 Build regular expression for module/task/function names.
TYPE is `module', `tf' for task or function, or t if unknown.
(defalias 'verilog-func-completion #[(type) "\306\230\203�\307	\310\267\202�\311\202�\312\202�\313\314\315R\316\317!\204^�\316\320\321\322
\f#\203U�\323 \211\203U�\324 \203U�\325
\203Q�`
V\202R�\320\204.�\326!\210\327\225,\210\330u\210eb\210d\320\331\332
\f#\203\225�\323 \211\203\225�\333 \203\225�\334
\203\221�`
W\202\222�\320\204n�\326!\210\327\225,\203\273�\335\224\335\225{ \203\262� \n!\203d�\n!B!\202d�\327\224\205\303�\327\224b*\207" [verilog-str type match verilog-defun-re NOERROR BOUND "" "[a-zA-Z_]" #s(hash-table size 2 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (module 14 tf 18)) "\\<\$module\$\\s +" "\\<\$task\\|function\$\\s +" "\\<\$task\\|function\\|module\$\\s +" "\\<\$" "[a-zA-Z0-9_.]*\$\\>" nil looking-at t (nil nil) re-search-backward match-data verilog-skip-backward-comment-or-string (nil nil) store-match-data 0 1 (nil nil) re-search-forward verilog-skip-forward-comment-or-string (nil nil) 2 REGEXP mdata verilog-pred verilog-all] 4 (#$ . 202242)])
#@145 Macro for searching through current declaration (var, type or const)
for matches of `str' and adding the occurrence tp `all' through point END.
(defalias 'verilog-get-completion-decl #[(end) "\203�	\206	�\n\306\211`W\203\320�
\307\310\311#\203M�\312 \211\203M�\313 \203M�\314\203I�`W\202J�\307\204\"�\315!\210\316\225,\203\320�\212\317 )\f\307\310\311#\203\225�\312 \211\203\225�\313 \203\225�\314\203\221�`W\202\222�\307\204j�\315!\210\316\225,\203\312�\320\225\204\312�\316\224\316\225{\321\322P\"\203]�\203\301�!\203]�B\202]�\320y\210\202�+\207" [verilog-indent-declaration-macros verilog-declaration-re-2-macro verilog-declaration-re-2-no-macro match decl-end re nil t (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) store-match-data 0 verilog-declaration-end 1 string-match "\\<" end NOERROR BOUND REGEXP mdata verilog-symbol-re verilog-str verilog-pred verilog-all] 4 (#$ . 203422)])
#@66 Calculate all possible completions for variables (or constants).
(defalias 'verilog-var-completion #[nil "`\301 \210\212\302!*\207" [start verilog-beg-of-defun verilog-get-completion-decl] 2 (#$ . 204435)])
#@68 Give list of all possible completions of keywords in KEYWORD-LIST.
(defalias 'verilog-keyword-completion #[(keyword-list) "\301\302\"\207" [keyword-list mapcar #[(s) "\304\305P	\"\205�\n\203�\n	!\205�	B\211\207" [verilog-str s verilog-pred verilog-all string-match "\\<"] 3]] 3 (#$ . 204650)])
#@540 Function passed to `completing-read', `try-completion' or `all-completions'.
Called to get completion on VERILOG-STR.  If VERILOG-PRED is non-nil, it
must be a function to be called for every match to check if this should
really be a match.  If VERILOG-FLAG is t, the function returns a list of
all possible completions.  If VERILOG-FLAG is nil it returns a string,
the longest possible completion, or t if VERILOG-STR is an exact match.
If VERILOG-FLAG is `lambda', the function returns t if VERILOG-STR is an
exact match, nil otherwise.
(defalias 'verilog-completion #[(verilog-str verilog-pred verilog-flag) "\212\306	q\210\307 @\211\310\267\202v�\212\311 \210)\312\313!\210\314!\210\202\204�\212\311 \210)\312\313!\210\314!\210\202\204�\212\311 \210)\312\315!\210\314\f!\210\202\204�\212\311 \210)\312\315!\210\314
!\210\202\204�\212\311 \210)\312\315!\210\314!\210\202\204�\212\311 \210)\314!\210\202\204�\212\311 \210)\202\204�\212\311 \210)\312\316!\210\314!\210)\317 *\207" [verilog-all verilog-buffer-to-use state verilog-defun-keywords verilog-block-keywords verilog-case-keywords nil verilog-calculate-indent #s(hash-table size 7 test eq rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (defun 16 behavioral 32 block 48 case 64 tf 80 cpp 97 cparenexp 110)) verilog-var-completion verilog-func-completion module verilog-keyword-completion tf both verilog-completion-response verilog-tf-keywords verilog-cpp-keywords verilog-separator-keywords] 3 (#$ . 204958)])
(defalias 'verilog-completion-response #[nil "\306=\204\n�\204e�	\205j�	A	@\211G\307\f\230\203%�\310\202T�\n\203T�\311\n@\"\211\fW\203=�
\312\313\f#\n@\f\230\203M�\310\307\211\202&�\nA\211\204)�\306=\205^�\310=??\205c�,\207\205j�	\207" [verilog-flag verilog-all elm match min tmp lambda nil t verilog-string-diff substring 0 verilog-str] 5])
(defvar verilog-last-word-numb 0)
(defvar verilog-last-word-shown nil)
(defvar verilog-last-completions nil)
#@125 Used as an element of `completion-at-point-functions'.
(See also `verilog-type-keywords' and
`verilog-separator-keywords'.)
(defalias 'verilog-completion-at-point #[nil "\212\306\307x\210`)\212\306\307w\210`)	{p\f\203%�
\n\230\203%�\n\202)�\310\n\311\"	E-\207" [b e verilog-str verilog-buffer-to-use verilog-toggle-completions verilog-last-word-shown "a-zA-Z0-9_" nil all-completions verilog-completion verilog-last-completions allcomp] 3 (#$ . 206927)])
#@133 Complete word at current point.
(See also `verilog-toggle-completions', `verilog-type-keywords',
and `verilog-separator-keywords'.)
(defalias 'verilog-complete-word #[nil "\306 \211@A@	\n{\3078
\203�\310\202!�\311\312\313\f\"\"	\n|\210
\203]�\f \fGSY\203;�\314\202>� T \f \234!\f\203R�\310!\261\202\346�\310\261\210\315\316!\202\346�\203i�\317=\203u�\310\261\210\315\316!\210\202{�\310\261\210\317=\203\223�\fA\203\215�\315\320!\202\346�\315\321!\202\346�\fA??\205\346�GGU\205\346�\"#r\322\323!q\210p\324 \210#\"\325\211$%\317\211&\317'(\326 \210\327\330!\210+\211)*\331\f!\210\332)!\210+\333\310`\"\210\334\325\335\323!\".\207" [comp-info b e verilog-str allcomp verilog-toggle-completions verilog-completion-at-point 2 "" try-completion mapcar #[(elm) "\301B\207" [elm 0] 2] 0 message "(No match)" t "(Complete but not unique)" "(Sole completion)" get-buffer-create "*Completions*" kill-all-local-variables nil erase-buffer run-hooks temp-buffer-setup-hook display-completion-list internal-temp-output-buffer-show momentary-string-display verilog-quit-window get-buffer-window match verilog-last-completions verilog-last-word-numb verilog-last-word-shown default-directory #1=#:old-dir buffer-read-only buffer-file-name buffer-undo-list inhibit-modification-hooks inhibit-read-only #2=#:buf standard-output] 6 (#$ . 207400) nil])
#@49 Show all possible completions at current point.
(defalias 'verilog-show-completions #[nil "r\306\307!q\210p\310 \210	\311\211\312\211\312\313 \210\314\315!\210+\211\316\317\320 8!\210\321!\210+\322\323`\"\210\324\311\325\307!\"\207" [default-directory #1=#:old-dir buffer-read-only buffer-file-name buffer-undo-list inhibit-modification-hooks get-buffer-create "*Completions*" kill-all-local-variables nil t erase-buffer run-hooks temp-buffer-setup-hook display-completion-list 2 verilog-completion-at-point internal-temp-output-buffer-show momentary-string-display "" verilog-quit-window get-buffer-window inhibit-read-only #2=#:buf standard-output] 5 (#$ . 208788) nil])
#@49 Return symbol around current point as a string.
(defalias 'verilog-get-default-symbol #[nil "\212\300\301x\210\302\301x\210`\302\301w\210`{)\207" [" 	" nil "a-zA-Z0-9_"] 3 (#$ . 209482)])
#@149 Return function/task/module starting with STR as regular expression.
With optional second ARG non-nil, STR is the complete name of the instruction.
(defalias 'verilog-build-defun-re #[(str &optional arg) "\204�	\302P\303	\304Q\207" [arg str "[a-zA-Z0-9_]*" "^\\s-*\$function\\|task\\|module\$[ 	]+\$?:\\(?:static\\|automatic\$\\s-+\\)?\$" "\$\\>"] 3 (#$ . 209677)])
#@561 Function passed to `completing-read', `try-completion' or `all-completions'.
Returns a completion on any function name based on VERILOG-STR prefix.  If
VERILOG-PRED is non-nil, it must be a function to be called for every match
to check if this should really be a match.  If VERILOG-FLAG is t, the
function returns a list of all possible completions.  If it is nil it
returns a string, the longest possible completion, or t if VERILOG-STR is
an exact match.  If VERILOG-FLAG is `lambda', the function returns t if
VERILOG-STR is an exact match, nil otherwise.
(defalias 'verilog-comp-defun #[(verilog-str verilog-pred verilog-flag) "\212\306\211\nq\210\211\307\230\203�\310\311!\202�\310!eb\210\306\312\313\314
\f#\203O�\315 \211\203O�\316 \203O�\317
\203K�`
W\202L�\312\204(�\320!\210\321\225,\203s�\322\224\322\225{\203l�!\203�	B\202�)\323 +\207" [match verilog-all verilog-buffer-to-use verilog-str NOERROR BOUND nil "" verilog-build-defun-re "[a-zA-Z_]" t (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) store-match-data 0 2 verilog-completion-response REGEXP mdata verilog-pred] 5 (#$ . 210059)])
#@190 Move to specified Verilog module/interface/task/function.
The default is a name found in the buffer around point.
If search fails, other files are checked based on
`verilog-library-flags'.
(defalias 'verilog-goto-defun #[nil "\304 p\305\230\204�\306\307\310Q\311\312\211\305%\202�\306\313\311\312\211\305%\312\314 \210\315 \210\n\305\230\2030�\n\305\230\206U�\212eb\210\316\317\n\320\"\312\320#)\203N�b\210\321 \210\206U�\322\n!,\207" [default verilog-buffer-to-use label pt verilog-get-default-symbol "" completing-read "Goto-Label: (default " ") " verilog-comp-defun nil "Goto-Label: " verilog-auto-reeval-locals verilog-getopt-flags re-search-forward verilog-build-defun-re t beginning-of-line verilog-goto-defun-file] 6 (#$ . 211242) nil])
#@33 List all scopes in this module.
(defalias 'verilog-showscopes #[nil "p\306\307\306e\310 \311&'(r\312\313!q\210p\314 \210('\315\211)*\316\211+\316,-\317 \210\320\321!\210+\211./\212\322\323\"\210\ndU\204u\315\316012\3243\325210#\203\201�\326 \2113\203\201�\327 \203\201�\33031\203}�`1W\202~�\316\204V�\3313!\210\307\225,\203u\307\224b\210\332 \210\326 4\333\216
\334\n`\"\\*`\307\225b\210\212\307\224b\210\f\307W\203\266�\f\202\270�\f[y\210`)5\212\307\225b\210\f\307V\203\320�\fTy\210\202\323�\306y\210`)6\335\336
\"7\3377G\340\"8\3159\212\310 \2119`\315\223\210/q\2109:B:\204\n\f\307U\204\n\341c\210\315\342&56#\21065Z\206\306[u\210\f\307W\203,\f[\202-\f\2119\307V\203G8\343\261\210\306y\2109S\2119\2020
;	`\307\225\307\224Z\\\315\223\210`	W\203p7\204g\335\336;\"77\343\261\210\202U.\202D�)\344\315!\345.!\210.\n\207" [regexp final-context-start prevpos first nlines linenum 1 0 make-marker "\$module\\s-+\\w+\\s-*(\$\\|\$\\w+\\s-+\\w+\\s-*(\$" get-buffer-create "*Occur*" kill-all-local-variables nil t erase-buffer run-hooks temp-buffer-setup-hook message "Searching for %s ..." (nil nil) re-search-forward match-data verilog-skip-forward-comment-or-string (nil nil) store-match-data beginning-of-line #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] count-lines format "%3d" make-string 32 "--------\n" insert-buffer-substring 58 set-buffer-modified-p internal-temp-output-buffer-show buffer default-directory #1=#:old-dir buffer-read-only buffer-file-name buffer-undo-list inhibit-modification-hooks inhibit-read-only #2=#:buf standard-output NOERROR BOUND REGEXP mdata save-match-data-internal start end tag empty tem occur-pos-list this-linenum] 8 (#$ . 212006) nil])
(defconst verilog-directive-regexp "\$translate\\|coverage\\|lint\$_")
#@56 Return point if within translate-off region, else nil.
(defalias 'verilog-within-translate-off #[nil "\212\301\302\303Q\304\305#)\205�\306\307!\310\232\205�`\207" [verilog-directive-regexp re-search-backward "//\\s-*.*\\s-*" "\$on\\|off\$\\>" nil t match-string 2 "off"] 4 (#$ . 213872)])
#@72 Return point before translate-off directive if before LIMIT, else nil.
(defalias 'verilog-start-translate-off #[(limit) "\302\303\304Q	\305#\205
�\306\224\207" [verilog-directive-regexp limit re-search-forward "//\\s-*.*\\s-*" "off\\>" t 0] 4 (#$ . 214172)])
#@72 Return point before translate-off directive if before LIMIT, else nil.
(defalias 'verilog-back-to-start-translate-off #[(limit) "\302\303\304Q	\305#\205
�\306\224\207" [verilog-directive-regexp limit re-search-backward "//\\s-*.*\\s-*" "off\\>" t 0] 4 (#$ . 214438)])
#@70 Return point after translate-on directive if before LIMIT, else nil.
(defalias 'verilog-end-translate-off #[(limit) "\302\303\304Q	\305#\207" [verilog-directive-regexp limit re-search-forward "//\\s-*.*\\s-*" "on\\>" t] 4 (#$ . 214713)])
#@101 Match a translate-off block, setting `match-data' and returning t, else nil.
Bound search by LIMIT.
(defalias 'verilog-match-translate-off #[(limit) "`W\205'�\304 \206�\305!\306\211\205&�\307!\206�\310\nD!\210b)*\207" [limit case-fold-search start end verilog-within-translate-off verilog-start-translate-off t verilog-end-translate-off set-match-data] 4 (#$ . 214959)])
#@155 Match, and move over, any declaration item after point.
Bound search by LIMIT.  Adapted from
`font-lock-match-c-style-declaration-item-and-skip-to-next'.
(defalias 'verilog-font-lock-match-item #[(limit) "\3021,�\214e}\210\303\304!\205)�\305 \306\216\307\225b\210\303\310!\203$�\307\225b\202(�\311\210\312*)0\207\210\311\207" [limit save-match-data-internal (error) looking-at "\\s-*\$[a-zA-Z]\\w*\$" match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] 1 "\$\\s-*,\$" nil t] 2 (#$ . 215348)])
#@96 Insert a standard Verilog file header.
See also `verilog-sk-header' for an alternative format.
(defalias 'verilog-header #[nil "`\304c\210b\210\305\306!\210\307\310 \311\211#\210\305\312!\210\307\313\311\211#\210\314 c\210\315\316 \317\320 \321\261\210\305\322!\210\307\313\311\211#\210\323 \210\305\324!\210\307\313\311\211#\210\323 \210\305\325!\210\307\313\311\211#\210\326 \210\305\327!\210\307\313\311\211#\210\323 \210\330c\210b\210\331\332\333!\305\334!\210\307	\311\211#\210\332\335\n\"\211\305\336!\210\307	\311\211#\210\332\337\"\211\305\340!\210\307	\311\211#\210\305\340!\210\307	\311\211#\210\305\340!\210\307	\311\211#\210\341\342!\210\307\313\311\211#*\207" [start string verilog-project verilog-company "//-----------------------------------------------------------------------------\n// Title         : <title>\n// Project       : <project>\n//-----------------------------------------------------------------------------\n// File          : <filename>\n// Author        : <author>\n// Created       : <credate>\n// Last modified : <moddate>\n//-----------------------------------------------------------------------------\n// Description :\n// <description>\n//-----------------------------------------------------------------------------\n// Copyright (c) <copydate> by <company> This model is the confidential and\n// proprietary property of <company> and the possession or use of this\n// file requires a written license from <company>.\n//------------------------------------------------------------------------------\n// Modification history :\n// <modhist>\n//-----------------------------------------------------------------------------\n\n" search-forward "<filename>" replace-match buffer-name t "<author>" "" user-full-name "  <" user-login-name "@" system-name ">" "<credate>" verilog-insert-date "<moddate>" "<copydate>" verilog-insert-year "<modhist>" " : created" nil read-string "title: " "<title>" "project: " "<project>" "Company: " "<company>" search-backward "<description>"] 6 (#$ . 215892) nil])
#@30 Insert date from the system.
(defalias 'verilog-insert-date #[nil "\203	�\301\302!c\207\301\303!c\207" [verilog-date-scientific-format format-time-string "%Y/%m/%d" "%d.%m.%Y"] 2 (#$ . 217944) nil])
#@30 Insert year from the system.
(defalias 'verilog-insert-year #[nil "\300\301!c\207" [format-time-string "%Y"] 2 (#$ . 218150) nil])
(defalias 'verilog-sig-new #[(name bits comment mem enum signed type multidim modport) "	\n\f
\257	\207" [name bits comment mem enum signed type multidim modport] 9])
(put 'verilog-sig-new 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-name #[(sig) "@\207" [sig] 1])
(put 'verilog-sig-name 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-bits #[(sig) "A@\207" [sig] 1])
(put 'verilog-sig-bits 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-comment #[(sig) "\3018\207" [sig 2] 2])
(put 'verilog-sig-comment 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-memory #[(sig) "\3018\207" [sig 3] 2])
(put 'verilog-sig-memory 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-enum #[(sig) "\3018\207" [sig 4] 2])
(put 'verilog-sig-enum 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-signed #[(sig) "\3018\207" [sig 5] 2])
(put 'verilog-sig-signed 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-type #[(sig) "\3018\207" [sig 6] 2])
(put 'verilog-sig-type 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-type-set #[(sig type) "\302\233	\240\207" [sig type 6] 2])
(put 'verilog-sig-type-set 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-multidim #[(sig) "\3018\207" [sig 7] 2])
(put 'verilog-sig-multidim 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-multidim-string #[(sig) "\3038)\205$�\304\3038)	\203\"�	@\nP	A\211\204�\n*\207" [sig args str 7 ""] 4])
(put 'verilog-sig-multidim-string 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-modport #[(sig) "\3018\207" [sig 8] 2])
(put 'verilog-sig-modport 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-sig-width #[(sig) "\301\211A@)!\207" [sig verilog-make-width-expression] 3])
(put 'verilog-sig-width 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-alw-new #[(outputs-del outputs-imm temps inputs) "\304	\n$\207" [outputs-del outputs-imm temps inputs vector] 5])
(put 'verilog-alw-new 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-alw-get-outputs-delayed #[(sigs) "\301H\207" [sigs 0] 2])
(put 'verilog-alw-get-outputs-delayed 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-alw-get-outputs-immediate #[(sigs) "\301H\207" [sigs 1] 2])
(put 'verilog-alw-get-outputs-immediate 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-alw-get-temps #[(sigs) "\301H\207" [sigs 2] 2])
(put 'verilog-alw-get-temps 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-alw-get-inputs #[(sigs) "\301H\207" [sigs 3] 2])
(put 'verilog-alw-get-inputs 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-alw-get-uses-delayed #[(sigs) "\301H\207" [sigs 0] 2])
(put 'verilog-alw-get-uses-delayed 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modport-new #[(name clockings decls) "	\nE\207" [name clockings decls] 3])
(put 'verilog-modport-new 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modport-name #[(sig) "@\207" [sig] 1])
(put 'verilog-modport-name 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modport-clockings #[(sig) "A@\207" [sig] 1])
(put 'verilog-modport-clockings 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modport-clockings-add #[(sig val) "A	A@B\240\207" [sig val] 3])
(put 'verilog-modport-clockings-add 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modport-decls #[(sig) "\3018\207" [sig 2] 2])
(put 'verilog-modport-decls 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modport-decls-set #[(sig val) "AA	\240\207" [sig val] 2])
(put 'verilog-modport-decls-set 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-new #[(name fob pt type) "\304	\n$\207" [name fob pt type vector] 5])
(put 'verilog-modi-new 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-name #[(modi) "\301H\207" [modi 0] 2])
(put 'verilog-modi-name 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-file-or-buffer #[(modi) "\301H\207" [modi 1] 2])
(put 'verilog-modi-file-or-buffer 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-get-point #[(modi) "\301H\207" [modi 2] 2])
(put 'verilog-modi-get-point 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-get-type #[(modi) "\301H\207" [modi 3] 2])
(put 'verilog-modi-get-type 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-get-decls #[(modi) "\301\302\"\207" [modi verilog-modi-cache-results verilog-read-decls] 3])
(put 'verilog-modi-get-decls 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-get-sub-decls #[(modi) "\301\302\"\207" [modi verilog-modi-cache-results verilog-read-sub-decls] 3])
(put 'verilog-modi-get-sub-decls 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-new #[(out inout in vars modports assigns consts gparams interfaces) "\306	\n\f
	&	\207" [out inout in vars modports assigns vector consts gparams interfaces] 10])
(put 'verilog-decls-new 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-append #[(a b) "\204�	\207	\204\f�\207\302\303\304H	\304H\"\303\305H	\305H\"\303\306H	\306H\"\303\307H	\307H\"\303\310H	\310H\"\303\311H	\311H\"\303\312H	\312H\"\303\313H	\313H\"\303\314H	\314H\"&	\207" [a b vector append 0 1 2 3 4 5 6 7 8] 13])
(put 'verilog-decls-append 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-get-outputs #[(decls) "\301H\207" [decls 0] 2])
(put 'verilog-decls-get-outputs 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-get-inouts #[(decls) "\301H\207" [decls 1] 2])
(put 'verilog-decls-get-inouts 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-get-inputs #[(decls) "\301H\207" [decls 2] 2])
(put 'verilog-decls-get-inputs 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-get-vars #[(decls) "\301H\207" [decls 3] 2])
(put 'verilog-decls-get-vars 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-get-modports #[(decls) "\301H\207" [decls 4] 2])
(put 'verilog-decls-get-modports 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-get-assigns #[(decls) "\301H\207" [decls 5] 2])
(put 'verilog-decls-get-assigns 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-get-consts #[(decls) "\301H\207" [decls 6] 2])
(put 'verilog-decls-get-consts 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-get-gparams #[(decls) "\301H\207" [decls 7] 2])
(put 'verilog-decls-get-gparams 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-decls-get-interfaces #[(decls) "\301H\207" [decls 8] 2])
(put 'verilog-decls-get-interfaces 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-subdecls-new #[(out inout in intf intfd) "\305	\n\f%\207" [out inout in intf intfd vector] 6])
(put 'verilog-subdecls-new 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-subdecls-get-outputs #[(subdecls) "\301H\207" [subdecls 0] 2])
(put 'verilog-subdecls-get-outputs 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-subdecls-get-inouts #[(subdecls) "\301H\207" [subdecls 1] 2])
(put 'verilog-subdecls-get-inouts 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-subdecls-get-inputs #[(subdecls) "\301H\207" [subdecls 2] 2])
(put 'verilog-subdecls-get-inputs 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-subdecls-get-interfaces #[(subdecls) "\301H\207" [subdecls 3] 2])
(put 'verilog-subdecls-get-interfaces 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-subdecls-get-interfaced #[(subdecls) "\301H\207" [subdecls 4] 2])
(put 'verilog-subdecls-get-interfaced 'byte-optimizer 'byte-compile-inline-expand)
#@76 Return signals in standard form from SIGNAME-LIST, a simple list of names.
(defalias 'verilog-signals-from-signame #[(signame-list) "\301\302\"\207" [signame-list mapcar #[(name) "\306\211\211\211\211\211\211\211	\211	
\f\n	\257	.	\207" [name modport multidim type signed enum nil mem comment bits] 10]] 3 (#$ . 226228)])
#@149 Return list of signals in IN-LIST that are also in NOT-LIST.
Also remove any duplicates in IN-LIST.
Signals must be in standard (base vector) form.
(defalias 'verilog-signals-in #[(in-list not-list) "\306\307\310\311\312$\306\307\310\311\313$\314\203#�\315@@\316	#\210A\211\204�\f\203V�\317\f@\211@)	\"\203O�\317\f@\211@)\n\"\204O�\f@B\315\f@\211@)\316\n#\210\fA\211\204'�\237+\207" [out-list ht-not ht not-list in-list sig make-hash-table :test equal :rehash-size 4.0 4.0 nil puthash t gethash] 7 (#$ . 226576)])
#@152 Return list of signals in IN-LIST that aren't also in NOT-LIST.
Also remove any duplicates in IN-LIST.
Signals must be in standard (base vector) form.
(defalias 'verilog-signals-not-in #[(in-list not-list) "\305\306\307\310\311$\312\n\203�\313\n@@\314	#\210\nA\211\204
�\203C�\315@\211@)	\"\204<�@B\313@\211@)\314	#\210A\211\204 �\237*\207" [out-list ht not-list in-list sig make-hash-table :test equal :rehash-size 4.0 nil puthash t gethash] 6 (#$ . 227112)])
#@214 Return list of signals in IN-LIST that aren't also in NOT-LIST.
Also remove any duplicates in IN-LIST.
Any structure in not-list will remove all members in in-list.
Signals must be in standard (base vector) form.
(defalias 'verilog-signals-not-in-struct #[(in-list not-list) "\306\307\310\311\312$\313\211\211\f\203 �\314\f@@\315#\210\fA\211\204�
\203j�
@\211@)\316\"\204c�\315\317\320\"\203N�\321\322\"	\205J�\316\"?\2025�	\203c�
@\nB\314
@\211@)\315#\210
A\211\204$�\n\237,\207" [nm addit out-list ht not-list in-list make-hash-table :test equal :rehash-size 4.0 nil puthash t gethash string-match "^\$[^\\].*\$\\.[^.]+$" match-string 1 sig] 6 (#$ . 227595)])
#@74 Return list of signals in IN-LIST that are memorized (multidimensional).
(defalias 'verilog-signals-memory #[(in-list) "\302	\203�\303	@8\203�	@B	A\211\204�)\207" [out-list in-list nil 3] 3 (#$ . 228289)])
#@37 Compare signal A and B for sorting.
(defalias 'verilog-signals-sort-compare #[(a b) "\211@)\n\211@)\231\207" [a sig b] 3 (#$ . 228509)])
#@80 Return list of signals in IN-LIST that aren't parameters or numeric constants.
(defalias 'verilog-signals-not-params #[(in-list) "\303	\203!�\304\305\306	@\211@)P!!\204�	@B	A\211\204�\237)\207" [out-list in-list sig nil boundp intern "vh-"] 5 (#$ . 228655)])
#@79 Return list of signals where FUNC is true executed on each signal in IN-LIST.
(defalias 'verilog-signals-with #[(func in-list) "\303	\203�\n	@!\203�	@B	A\211\204�\237)\207" [out-list in-list func nil] 3 (#$ . 228928)])
#@137 Return a list of signals in IN-LIST, with buses combined.
Duplicate signals are also removed.  For example A[2] and A[1] become A[2:1].
(defalias 'verilog-signals-combine-bus #[(in-list) "\306\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211 !\"#$%&'()\307*\310\"**\203*@&#\204\243�&\211&@)#\306\211\"&&\311&8) &&\312&8)&&\313&8)&&\314&8)&&\315&8)&&\316&8)&&\317&8)\320\211)(&\211&A@)\211\205\263�\321!\211\203\n\322\323\"\203\323�\324\325\326\"!%\324\325\311\"!\211$\204\351�\322\327\"\203\n\324\325\326\"!\211%\211$\203\n\"\203\377�%\"]\"$!^!\202%\"$!\202\203*A\211*@\211&\203\250#&\211&@)\232\203\250\n\203>\n&\211&A@)\232\204>\330(&&\311&8)\203M\331)\206[&&\312&8)\206k&&\313&8)
\206z&&\314&8)\f\206\210&&\315&8)\206\226&&\316&8)	\206\244&&\317&8)\2027�#\n\206\300\"\205\300\332\333\"!\334\333!!\335\260 )(Q
\f	+,-./012\2113210/.-,+\257	.	'B'\306#\2027�'.\207" [bus sv-modport sv-busstring sv-multidim sv-type sv-signed nil sort verilog-signals-sort-compare 2 3 4 5 6 7 8 "" verilog-simplify-range-expression string-match "^\\[\$[0-9]+\$:\$[0-9]+\$\\]$" string-to-number match-string 1 "^\\[\$[0-9]+\$\\]$" ", Couldn't Merge" ", ..." "[" int-to-string ":" "]" sv-enum sv-memory sv-comment sv-lowbit sv-highbit sv-name lowbit highbit sig out-list buswarn combo in-list modport multidim type signed enum mem comment bits name] 19 (#$ . 229162)])
#@144 Return tieoff expression for given SIG, with appropriate width.
Tieoff value uses `verilog-active-low-regexp' and
`verilog-auto-reset-widths'.
(defalias 'verilog-sig-tieoff #[(sig) "\203�	\211@)\306
\307\f\n#,\203�\310\202�\311\204(�\312\202j�\313=\2033�\314\202j�	\315	\211A@)!)\211\204H�\316\202i�\307\317\"\203d�	\320	8)\203_�\321\202`�\322P\202i�\323\324Q)P\207" [verilog-active-low-regexp sig start string regexp verilog-case-fold nil string-match "~" "" "0" unbased "'0" verilog-make-width-expression "`0/*NOWIDTH*/" "^[0-9]+$" 5 "'sh0" "'h0" "{" "{1'b0}}" case-fold-search verilog-auto-reset-widths width] 5 (#$ . 230736)])
#@91 For debug, dump the `verilog-read-decls' structure DECLS.
Use optional HEADER and PREFIX.
(defalias 'verilog-decls-princ #[(decls &optional header prefix) "\205\234�	\203\f�\303	!\210\n\206�\304\305\211\306H)\n\307P\n\310P#\210\305\211\311H)\n\312P\n\310P#\210\305\211\313H)\n\314P\n\310P#\210\305\211\315H)\n\316P\n\310P#\210\305\211\317H)\n\320P\n\310P#\210\305\211\321H)\n\322P\n\310P#\210\305\211\323H)\n\324P\n\310P#\210\305\211\325H)\n\326P\n\310P#\210\327\211\330H)\n\331P\n\310P#\210\303\332!\207" [decls header prefix princ "" verilog-signals-princ 0 "Outputs:\n" "  " 1 "Inout:\n" 2 "Inputs:\n" 3 "Vars:\n" 5 "Assigns:\n" 6 "Consts:\n" 7 "Gparams:\n" 8 "Interfaces:\n" verilog-modport-princ 4 "Modports:\n" "\n"] 6 (#$ . 231400)])
#@70 For debug, dump internal SIGNALS structures, with HEADER and PREFIX.
(defalias 'verilog-signals-princ #[(signals &optional header prefix) "\205\232�	\203\f�\304	!\210\205\232�@A\304!\210\304\305!\210\304\n\211@)!\210\304\305!\210\304\306!\210\304\n\211A@)!\210\304\307!\210\304\n\310\n8)!\210\304\311!\210\304\n\312\n8)!\210\304\313!\210\304\n\314\n8)!\210\304\315!\210\304\n\316\n8)!\210\304\317!\210\304\n\320\n8)!\210\304\321!\210\304\n\322\n8)!\210\304\323!\210\304\n\324\n8)!\210\304\325!\210)\202\f�\207" [signals header sig prefix princ "\"" "  bits=" "  cmt=" 2 "  mem=" 3 "  enum=" 4 "  sign=" 5 "  type=" 6 "  dim=" 7 "  modp=" 8 "\n"] 4 (#$ . 232168)])
#@71 For debug, dump internal MODPORTS structures, with HEADER and PREFIX.
(defalias 'verilog-modport-princ #[(modports &optional header prefix) "\205N�	\203\f�\304	!\210\205N�@A\304!\210\304\305!\210\304\n\211@)!\210\304\305!\210\304\306!\210\304\n\211A@)!\210\304\307!\210\310\n\311\n8)\312P\313P#\210)\202\f�\207" [modports header sig prefix princ "\"" "  clockings=" "\n" verilog-decls-princ 2 "  syms:\n" "    "] 6 (#$ . 232854)])
#@55 Internal.  Move point back to beginning of inst-name.
(defalias 'verilog-read-inst-backward-name #[nil "\305 \210\306\204I�\307\306\211\306\f\2044�\310\n	#\2034�\311\312\224!\203-�\310\313\306\314#\210\202�\312\224\211\203�\f,\210\315\316!\203C�\305 \210\202�\314\211\203	�)\315\317!\203\204�\320 \210\321\306\211\306\f\204~�\310\n	#\203~�\311\312\224!\203w�\310\313\306\314#\210\202[�\312\224\211\203_�\f,\210\202J�\322\306x\207" [done noerror bound regexp pt verilog-backward-open-paren nil "\$)\\|\\b[a-zA-Z0-9`_$]\\|\\]\$" re-search-backward verilog-inside-comment-or-string-p 0 "[/\"]" t looking-at ")" "\\]" verilog-backward-open-bracket "\$\\b[a-zA-Z0-9`_$]\\|\\]\$" "a-zA-Z0-9`_$"] 5 (#$ . 233303)])
#@71 Set match data 0 with module_name when point is inside instantiation.
(defalias 'verilog-read-inst-module-matcher #[nil "\304 \210\305\306\211\306\204.�\307\n	#\203.�\310\311\224!\203'�\307\312\306\313#\210\202�\311\224\211\203�,\210\314\315!\203h�\316 \210\317\306\211\306\204e�\307\n	#\203e�\310\311\224!\203^�\307\312\306\313#\210\202B�\311\224\211\203F�,\210\320\306x\210\212\321 \210`Sf)\322=\203\253�\317\306\211\306\204\244�\307\n	#\203\244�\310\311\224!\203\235�\307\312\306\313#\210\202\201�\311\224\211\203\205�,\210\320\306x\210\314\323!\210\324\311\224\311\225\"\207" [noerror bound regexp pt verilog-read-inst-backward-name "\$\\b[a-zA-Z0-9`_$]\\|)\$" nil re-search-backward verilog-inside-comment-or-string-p 0 "[/\"]" t looking-at ")" verilog-backward-open-paren "\\b[a-zA-Z0-9`_$]" "a-zA-Z0-9`_$" verilog-backward-syntactic-ws-quick 35 "[a-zA-Z0-9`_$]+" buffer-substring-no-properties] 4 (#$ . 234039)])
#@56 Return module_name when point is inside instantiation.
(defalias 'verilog-read-inst-module #[nil "\212\300 )\207" [verilog-read-inst-module-matcher] 1 (#$ . 234993)])
#@58 Return instance_name when point is inside instantiation.
(defalias 'verilog-read-inst-name #[nil "\212\300 \210\301\302!\210\303\304\224\304\225\")\207" [verilog-read-inst-backward-name looking-at "[a-zA-Z0-9`_$]+" buffer-substring-no-properties 0] 3 (#$ . 235166)])
#@43 Return module name when after its ( or ;.
(defalias 'verilog-read-module-name #[nil "\212\305\306!\210\307\211\307\f\2040�\305\n	#\2030�\310\311\224!\203)�\305\312\307\313#\210\202
�\311\224\211\203�\f,\210\311\225b\210\314\307\211\307\f\204b�\315\n	#\203b�\310\311\224!\203[�\315\316\307\313#\210\202?�\311\225\211\203C�\f,\210\317\320\311\224\311\225\"\313\")\207" [verilog-defun-re noerror bound regexp pt re-search-backward "[(;]" nil verilog-inside-comment-or-string-p 0 "[/\"]" t "\\b[a-zA-Z0-9`_$]+" re-search-forward "[/\"\n]" verilog-symbol-detick buffer-substring-no-properties] 4 (#$ . 235439)])
#@74 Return list of parameters and values when point is inside instantiation.
(defalias 'verilog-read-inst-param-value #[nil "\212\306 \210\307\310\211\310\204/�\311\n	#\203/�\312\313\224!\203(�\311\314\310\315#\210\202\f�\313\224\211\203�,\210\316\317!\205\205`\310\211\211\211!\"#\320 \210\321#\315\310\204t�\322\n	#\203t�\312\313\224!\203m�\322\323\310\315#\210\202Q�\313\225\211\203U�,\203\202\324\310\211\310\204\244�\322\n	#\203\244�\312\313\224!\203\235�\322\323\310\315#\210\202\201�\313\225\211\203\205�,\210\325\310x\210\316\326!\210\327\313\224\313\225\"!\330\310\211\310\204\342�\322\n	#\203\342�\312\313\224!\203\333�\322\323\310\315#\210\202\277�\313\225\211\203\303�,\210`\331 \210\327
`S\"$\332 %\333\216\334\335\310\211$$&'()\313*\336)$*#\203/\337('&$$\211$G\313\224(G\\^*\202\n$.$\340\335\310\211$$&'()\313*\336)$*#\203m\337('&$$\211$G\313\224(G\\^*\202H$.\211$+!\fD\"B\"\202H�\"-)\207" [noerror bound regexp pt param-value paren-beg-pt verilog-read-inst-backward-name "\$\\b[a-zA-Z0-9`_$]\\|)\$" nil re-search-backward verilog-inside-comment-or-string-p 0 "[/\"]" t looking-at ")" verilog-backward-open-paren "\\." re-search-forward "[/\"\n]" "\$[a-zA-Z0-9`_$]\$" "a-zA-Z0-9'_$" "[a-zA-Z0-9`_$]+" buffer-substring-no-properties "(" verilog-forward-close-paren match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] "^\\s-+" "" string-match replace-match "\\s-+$" param-name params end-pt string save-match-data-internal literal fixedcase to-string from-string start] 5 (#$ . 236066)])
#@112 Return parameter list inside auto.
Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters.
(defalias 'verilog-read-auto-params #[(num-param &optional max-param) "\303\212\304\305!\210\306\307!\2036�\305\303\224\205*�\211\203$�\310\224\225#\266\202\202,�\311\224\225\"\266\202B\312\225b\210\202�)	\303=\204K�	GX\204K�\313\314\315 	#\210\n\303=\203S�	\n\303=\204g�\nGY\204g�\313\316\315 \n#\210\237)\207" [olist num-param max-param nil backward-sexp 1 looking-at "(?\\s *\"\$[^\"]*\$\"\\s *,?" substring-no-properties buffer-substring-no-properties 0 error "%s: Expected %d parameters" verilog-point-text "%s: Expected <= %d parameters"] 6 (#$ . 237705)])
#@139 Compute signal declaration information for the current module at point.
Return an array of [outputs inouts inputs wire reg assign const].
(defalias 'verilog-read-decls #[nil "\306 \206�d\307\211\211\310\311\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211@ABCDEFGHI;>=<:98JKLMNOPQRS\212\312 \210\313`S\">`SW\203\205\314\315!\203\250�\314\316!\203\241�\317\311\224\205\235�\211\203\227�\320\224\225#\266\202\202\237�\321\224\225\"\266\202A\322\323!\210\202|\314\324!\203\350�\317u\210\314\316!\203\330�\317\311\224\205\324�\211\203\316�\320\224\225#\266\202\202\326�\321\224\225\"\266\202A\322\325!\204|\326\327\330 `#\210\202|\314\331!\203\374�\332\333\311\310#\204|\311y\210\202|\314\334!\203\332\335\311\310#\204|\311y\210\202|\314\336!\203)\337u\210\322\340!\204|\326\341\330 `#\210\202|g\342=\203A\332\343\311\310#\204|\326\344\330 `#\210\202|g\345=\203\370L\203U\311\211LB\202\362N\203\327N\310=\204\327N9:8\311\211\211\211\211\211TUVWXYZ[\\\346\\[ZYXWVUT&	.	]\211^AA]\240*\210	@	A\307H9\337H:\317H8\311\211G@\311\211FC\307Q\311\211BO\311\211NJ\202\362\311\211G@\311\211FC\307Q\311\211BO\311\211NJ\337u\210\202|g\347=\203\n\310B\311C\337u\210\202|g\350=\203!QP=\203!\311B\337u\210\202|\314\351!\2032QTQ\337u\210\202|\314\352!\203QQSQ\337u\210QPW\203|\311\211FB\202|\314\353!\203\321`\354\337!\210`\"EC\203\215CAAAC^\355^8)\203\206C^\355^8)EP\202\210E\240\210\202|G\203\330GB\356\357\311\211E_`abc\307d\360c_d#\203\317\361ba`_$\211_G\307\224bG\\^d\202\252_.G\202|\356\357\311\211E_`abc\307d\360c_d#\203\361ba`_$\211_G\307\224bG\\^d\202\353_.G\202|\314\362!\203y\307\225b\210ED\337\311\224\205D\211\203>\320\224\225#\266\202\202F\321\224\225\"\266\202E\360\363\337\311\224\205g\211\203a\320\224\225#\266\202\202i\321\224\225\"\266\202\"\203sE\364PE\314\365!\203\320\307\225b\210E\366\337\311\224\205\235\211\203\227\320\224\225#\266\202\202\237\321\224\225\"\266\202QE\360\363\337\311\224\205\301\211\203\273\320\224\225#\266\202\202\303\321\224\225\"\266\202\"\203sE\364PE\202sE\367\267\202\371\311\211GA\311\211BC\311\211\311\211K\311\370F\310@QP\202|\311\211GA\311\211BC\311\211\311\211K\311\371F\310@QP\202|\311\211GA\311\211BC\311\211\311\211K\311\372F\310@QP\202|\311\211GA\311\211B\311\211\311\211K\373F\310@QP\202|@\203{\f\203u\f\364EQ\202wE\202|\311\211GA\311\211B\311\211QP\374F\311\202|\311\211GA\311\211B\311\211\311\211K\375FQP\202|\311\211GA\311\211B\311\211\311\211K\376FQP\202|E\202|\310J\202|J\204|RTR\202|RSR\202|\310N\202|E\377\232\203D\201m�\232\204\310M\202|E\201n�\267\202;O\203|\310\211LB\202|\310K\202|\202|\310B\202|\311y\210\202|K\204|\201o�E!\203|@\203`\f\203Z\f\364EQ\202\\E\202|\311\211GA\311\211BE\311QP\374F\311\202|O\203\353Q\337=\203\353B\204\353\314\201p�!\204\235\314\201q�!\203\353\317\225\203\246\317\225b\210\311\211GA\311\211BE\311\211K\317\311\224\205\326\211\203\320\320\224\225#\266\202\202\330\321\224\225\"\266\202\311CQP\201I�F\310@\202|\314\201r�!\203\307\225b\210B\204|\311F\202|N\310=\203AEe\235\204AE\311\211fg\211hgfE+\211NHBH\3469:8#	B\311\2118:\3119\202|N\203eM\203eNE]\211^A]^A@B\240*\210\311M\202|M\203\330E\201s�\232\203\330M\310=\204\322M9:8\311\211\211\211\211\211TUVWXYZ[\\\346\\[ZYXWVUT&	.	]\211^AA]\240*\210	@	A\307H9\337H:\317H8\311M\202|M\310=\203Ee\235\204E\311\211fg\211hgfE+\211MHBH\3469:8#	B\311\2118:\3119\202|F\203|B\204|R\307=\203|Ee\235\204|@\203=QP=\203|EG\311\211A
\f\niAjkl\211hlkjA
i\n\257	.	CFCFJBL\210\202|\337u\210\201t�\364!\210\202m�9\237:\2378\237<\237H\237=\237>\237;\237I\237TUVWXYZ[\\\346\\[ZYXWVUT&	.	\211.\"\207" [tmp varstack modport multidim typedefed signed verilog-get-end-of-defun 0 t nil verilog-beg-of-defun-quick verilog-read-auto-constants looking-at "//" "[^\n]*\$auto\\|synopsys\$\\s +enum\\s +\$[a-zA-Z0-9_]+\$" 2 substring-no-properties buffer-substring-no-properties search-forward "\n" "/\\*" "*/" error "%s: Unmatched /* */, at char %d" verilog-point-text "^\\s *`pragma\\s +protect\\s +begin_protected" re-search-forward "^\\s *`pragma\\s +protect\\s +end_protected" "^\\s *`protected\\>" "^\\s *`endprotected\\>" "(\\*" 1 "*)" "%s: Unmatched (* *), at char %d" 34 "[^\\]\"" "%s: Unmatched quotes, at char %d" 59 vector 61 44 "[{(]" "[})]" "\\[" forward-sexp 3 "\\s-+" "" string-match replace-match "\\s-*\$[a-zA-Z0-9`_$]+\\|\\\\[^ 	\n\f]+\$" "^\\\\" " " "\\s-*::\\s-*\$\\*\\|[a-zA-Z0-9`_$]+\\|\\\\[^ 	\n\f]+\$" "::" #s(hash-table size 55 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("input" 983 "output" 1019 "inout" 1055 "parameter" 1091 "wire" 1124 "reg" 1124 "tri" 1124 "tri0" 1124 "tri1" 1124 "triand" 1124 "trior" 1124 "trireg" 1124 "uwire" 1124 "wand" 1124 "wor" 1124 "byte" 1124 "shortint" 1124 "int" 1124 "longint" 1124 "integer" 1124 "time" 1124 "supply0" 1124 "supply1" 1124 "bit" 1124 "logic" 1124 "shortreal" 1124 "real" 1124 "realtime" 1124 "string" 1124 "event" 1124 "chandle" 1124 "assign" 1174 "localparam" 1204 "genvar" 1204 "signed" 1234 "unsigned" 1234 "assert" 1240 "assume" 1240 "cover" 1240 "expect" 1240 "restrict" 1240 "class" 1246 "covergroup" 1246 "function" 1246 "property" 1246 "randsequence" 1246 "sequence" 1246 "task" 1246 "endclass" 1259 "endgroup" 1259 "endfunction" 1259 "endproperty" 1259 "endsequence" 1259 "endtask" 1259 "modport" 1267)) sigs-in sigs-out sigs-inout sigs-gparam sigs-var sigs-assign sigs-const "clocking" io enum rvalue newsig last-keywd keywd expect-signal vec sigs-modports sigs-intf ign-prop ptype in-ign-to-semi in-clocking in-modport v2kargs-ok sig-paren paren functask end-mod-point interfaces gparams consts assigns modports vars in inout out val sig string literal fixedcase to-string from-string start verilog-keywords decls clockings name type mem comment bits "default" #s(hash-table size 7 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("import" 1304 "type" 1318 "var" 1324 "`ifdef" 1327 "`ifndef" 1327 "`elsif" 1327 "`line" 1333)) verilog-typedef-name-p "\\s-*#" "\\s-*\$\\.\\(\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*\$\\|\\)\\s-*[a-zA-Z`_$][a-zA-Z0-9`_$]*" "\\s-*\\." "endclocking" skip-syntax-forward] 34 (#$ . 238402)])
#@78 For `verilog-read-sub-decls', process next signal as under interfaced block.
(defvar verilog-read-sub-decls-in-interfaced nil (#$ . 245143))
#@77 For `verilog-read-sub-decls', gate IO pins remaining, nil if non-primitive.
(defvar verilog-read-sub-decls-gate-ios nil (#$ . 245290))
#@58 For `verilog-read-sub-decls-line', decode a signal type.
(defalias 'verilog-read-sub-decls-type #[(par-values portdata) "\305	8)\306\n\"\n\307\235\203�\310\202!�\f\203 �\fA@\202!�\n*\207" [portdata sig type par-values pvassoc 6 assoc ("wire" "reg") nil] 3 (#$ . 245431)])
#@50 For `verilog-read-sub-decls-line', add a signal.
(defalias 'verilog-read-sub-decls-sig #[(submoddecls par-values comment port sig vec multidim mem) "\306=\307\205>\310!\n\203�\202�\310!\f\203\"�\310\f!
\203+�\311\310
\"\2036�\310!?\206>�\312\232?\205>\313\211\314H)\"\211\204Y�\315\232\203\252�\n\203g�	\211A@)\202h�\f\316P\307	\3178)\320	\"
\307 !\"#\211$#\"! 
\257	.	%B\211%\202>\313\211\321H)\"\211\204\301�\322\232\203\n\203\317�	\211A@)\202\320�\f\323P\307	\3178)\320	\"
\307 !\"#\211$#\"! 
\257	.	&B\211&\202>\313\211\324H)\"\211\204)\325\232\203z\n\2037	\211A@)\2028\f\326P\307	\3178)\320	\"
\307 !\"#\211$#\"! 
\257	.	'B\211'\202>\313\211\327H)\"\211\203\333\n\203\230	\211A@)\202\231\f\316P\307	\3178)\320	\"
\307 !\"#\211$#\"! 
\257	.	(B\211(\202>)\205\353\313\211\330H)\"\211\205>\n\203\376	\211A@)\202\377\f\316P\307	\3178)\320	\"
\307 !\"#\211$#\"! 
\257	.	(B\211**\207" [sig portdata dotname port vec multidim t nil verilog-symbol-detick-denumber mapcar "" assoc 1 "inout" "To/From " 5 verilog-read-sub-decls-type 0 "output" "From " 2 "input" "To " 8 3 mem submoddecls decls verilog-read-sub-decls-gate-ios comment par-values modport type signed enum bits name sigs-inout sigs-out sigs-in sigs-intf verilog-read-sub-decls-in-interfaced sigs-intfd] 10 (#$ . 245715)])
#@75 For `verilog-read-sub-decls-line', parse a subexpression and add signals.
(defalias 'verilog-read-sub-decls-expr #[(submoddecls par-values comment port expr) "\306\307\310\211\311!\312
	!#\203*�\313\f\n	$\211G\311\224\fG\\^!\202
�	.\314\315\310\211\311!\312
	!#\203X�\313\f\n	$\211G\311\224\fG\\^!\202;�	.\312\316\"\203\216�\317\320\321\"\322\"\310\"##\211A#\242\211\"\205\214�\323$%&'\"%\210\202o�*\207\310\211\211\211()*+\314\315\310\211\311!\312
	!#\203\304�\313\f\n	$\211G\311\224\fG\\^!\202\247�	.\324\315\310\211\311!\312
	!#\203\362�\313\f\n	$\211G\311\224\fG\\^!\202\325�	.\325\307\310\211\311!\312
	!#\203 \313\f\n	$\211G\311\224\fG\\^!\202	.\312\326\"\203:\320\321\"+\327\311\225\"\202\262\312\330\"\203\262\320\321\"\331 ,\332\216\333\315\310\211	\311!\312
	!#\203v\313\f\n	$\211G\311\224\fG\\^!\202Y	.\334\315\310\211	\311!\312
	!#\203\244\313\f\n	$\211G\311\224\fG\\^!\202\207	.\211++\327\311\225\"\312\335\"\203\324*\203\305*)B)\320\321\"*\327\311\225\"\202\262\312\336\"\203\352\320\321\"(\327\311\225\"\202\324+\205	\312\337\"\205	\340$%&'+*)(&,\207" [expr string literal fixedcase to-string from-string "/\\*\$\\.?\\[[^*]+\\]\$\\*/" "\\1" nil 0 string-match replace-match "^\\s-*[---+~!|&]+\\s-*" "" "^\\s-*{\$.*\$}\\s-*$" split-string match-string 1 "[{},]" verilog-read-sub-decls-expr "^\\s-*[a-zA-Z_][a-zA-Z_0-9]*\\s-*'" "^\\s-*(\$[^)]*\$)\\s-*$" "^\\s-*\$\\\\[^ 	\n\f]+\\s-\$" substring "^\\s-*\$[a-zA-Z_][a-zA-Z_0-9]*\$" match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] "^\\s-+" "\\s-+$" "^\\s-*\$\\[\\([^][]+\\|\\[[^][]+\\]\$*\\]\\)" "^\\s-*\\.\$\\(\\[[^]]+\\]\$+\\)" "^\\s-*$" verilog-read-sub-decls-sig start mstr mlst submoddecls par-values comment port mem multidim vec sig save-match-data-internal] 9 (#$ . 247249)])
#@144 For `verilog-read-sub-decls', read lines of port defs until none match.
Inserts the list of signals found, using submodi to look up each port.
(defalias 'verilog-read-sub-decls-line #[(submoddecls par-values comment) "\306\211\212\307y\210	?\205\246\310\311!\203:�\307\306\224\2050�\211\203*�\312\224\225#\266\202\2022�\313\224\225\"\266\202\314\225b\210\202\350�\310\315!\203i�\307\306\224\205]�\211\203W�\312\224\225#\266\202\202_�\313\224\225\"\266\202\316P\314\225b\210\202\350�\310\317!\203\236�\320\n\f\307\306\224\205\220�\211\203\212�\312\224\225#\266\202\202\222�\313\224\225\"\266\202\321\306\211\211&\210\306\202\350�\310\322!\203\325�\320\n\f\307\306\224\205\305�\211\203\277�\312\224\225#\266\202\202\307�\313\224\225\"\266\202\316P\321\306\211\211&\210\306\202\350�\310\323!\203\344�\306\314\225b\210\202\350�\306\321\203\240
\203\366�\310\324!\204\240\310\325!\203\257\320\n\f\307\306\224\205\211\203\312\224\225#\266\202\202 \313\224\225\"\266\202$\326 %\327\216\330\331\306\211$$&'()\314*\332)$*#\203`\333('&$$\211$G\314\224(G\\^*\202;$.$\334\331\306\211$$&'()\314*\332)$*#\203\236\333('&$$\211$G\314\224(G\\^*\202y$.\211$+\306\211\211&\210\202\240\310\335!\203\206\320\n\f\307\306\224\205\327\211\203\321\312\224\225#\266\202\202\331\313\224\225\"\266\202$\326 %\327\216\330\331\306\211$$&'()\314*\332)$*#\203\333('&$$\211$G\314\224(G\\^*\202\364$.$\334\331\306\211$$&'()\314*\332)$*#\203W\333('&$$\211$G\314\224(G\\^*\2022$.\211$+\336\306\224\205|\211\203v\312\224\225#\266\202\202~\313\224\225\"\266\202\306\211&\210\202\240\310\337!\203\240\340\n\f\313`\341\342!\210\343\307!\210`S\"%\210\307y\210\202�+\207" [port done submoddecls par-values comment verilog-auto-ignore-concat nil 1 looking-at "\\s-*\\.\\s-*\$[a-zA-Z0-9`_$]*\$\\s-*(\\s-*" substring-no-properties buffer-substring-no-properties 0 "\\s-*\\.\\s-*\$\\\\[^ 	\n\f]*\$\\s-*(\\s-*" " " "\\s-*\\.\\s-*\$[a-zA-Z0-9`_$]*\$\\s-*[,)/]" verilog-read-sub-decls-sig t "\\s-*\\.\\s-*\$\\\\[^ 	\n\f]*\$\\s-*[,)/]" "\\s-*\\.[^(]*(" "[({]" "\$[a-zA-Z_][a-zA-Z_0-9]*\$\\s-*)" match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] "^\\s-+" "" string-match replace-match "\\s-+$" "\$[a-zA-Z_][a-zA-Z_0-9]*\$\\s-*\$\\[[^][]+\\]\$\\s-*)" 2 "[^)]+" verilog-read-sub-decls-expr search-backward "(" verilog-forward-sexp-ign-cmt string save-match-data-internal literal fixedcase to-string from-string start] 12 (#$ . 249215)])
#@112 For `verilog-read-sub-decls', read lines of UDP gate decl until none match.
Inserts the list of signals found.
(defalias 'verilog-read-sub-decls-gate #[(submoddecls par-values comment submod end-inst-point) "\212\306	\"A`W\205\222�\307\310!\203�\311\312!\210\202�\307\313!\2030�\311\314!\204�\315\316\317 `#\210\202�\307\320!\203I�\321u\210\311\322!\204�\315\323\317 `#\210\202�\307\324!\203\210�\325\225b\210\n@\206Y�\326\nA\327
\330\325\331\224\205\201�\211\203{�\332\224\225#\266\202\202\203�\333\224\225\"\266\202%\210\202�\321u\210\334\335!\210\202�*\207" [submod verilog-gate-ios iolist end-inst-point verilog-read-sub-decls-gate-ios submoddecls assoc looking-at "//" search-forward "\n" "/\\*" "*/" error "%s: Unmatched /* */, at char %d" verilog-point-text "(\\*" 1 "*)" "%s: Unmatched (* *), at char %d" "\\s-*[a-zA-Z0-9`_$({}\\][^,]*" 0 "input" verilog-read-sub-decls-expr "primitive_port" nil substring-no-properties buffer-substring-no-properties skip-syntax-forward " " par-values comment] 11 (#$ . 251837)])
#@771 Internally parse signals going to modules under this module.
Return an array of [ outputs inouts inputs ] signals for modules that are
instantiated in this module.  For example if declare A A (.B(SIG)) and SIG
is an output, then SIG will be included in the list.

This only works on instantiations created with /*AUTOINST*/ converted by
\[verilog-auto-inst].  Otherwise, it would have to read in the whole
component library to determine connectivity of the design.

One work around for this problem is to manually create // Inputs
and // Outputs comments above subcell signals, then have an empty
AUTOINST, for example:

submod SubModuleName (
            // Outputs
            .out (out),
            // Inputs
            .in  (in)
            /*AUTOINST*/);
(defalias 'verilog-read-sub-decls #[nil "\212\306 \307\211\211\211\211\211\211\211$%&\310 \210\311&\312'()\307**\204O�\313)('#\203O�\314\315\224!\203G�\313\316\307\312#\210\202'�\315\225\211*\203,�*,\203\226\212\315\224b\210+\205f�,\205f�\317 \314 \204\222\320 -\321 .-/\2350.\322-\323R1\307\211230\203\357�\3242\307\211\211\211\211\211\211\211\211456789:;<\325<;:987654&	.	3.\322-Q1\326 \210\212\327\330!\210`)$`%\330u\210\3313
1-$%\210\202\220\332-\312\"\2112\203\2202=\333=\334\")3\307>\326 \210\212\327\330!\210`)$`%\312?\313\335$\312#\203/\3363
1#\210\202)%b\210\313\337$\312#\203H\3363
1#\210\2024%b\210\313\340$\312#\203`\3363
1#\210\202L%b\210\313\341$\312#\203x\3363
1#\210\202d%b\210\313\342$\312#\203\220\3363
1#\210\202|.)\202�\343\f\237!\343\237!\343\n\237!\343	\237!\343\237!@A:;<\325<;:A@%.\207" [sigs-intfd sigs-intf sigs-in sigs-inout sigs-out par-values verilog-get-end-of-defun nil verilog-beg-of-defun-quick "\$/\\*AUTOINST\\((.*?)\$?\\*/\\|\\.\\*\\)" t re-search-forward verilog-inside-comment-or-string-p 0 "[/\"\n]" verilog-read-inst-param-value verilog-read-inst-module verilog-read-inst-name " of " ".v" primitive vector verilog-backward-open-paren verilog-forward-sexp-ign-cmt 1 verilog-read-sub-decls-gate verilog-modi-lookup verilog-modi-cache-results verilog-read-decls "\\s *(?\\s *// Interfaced" verilog-read-sub-decls-line "\\s *(?\\s *// Interfaces" "\\s *(?\\s *// Outputs" "\\s *(?\\s *// Inouts" "\\s *(?\\s *// Inputs" verilog-signals-combine-bus end-inst-point st-point end-mod-point noerror bound regexp pt verilog-auto-inst-param-value verilog-auto-inst-param-value-type submod inst verilog-gate-keywords subprim comment submodi submoddecls interfaces gparams consts assigns modports vars in inout out modi verilog-read-sub-decls-gate-ios verilog-read-sub-decls-in-interfaced intfd intf] 11 (#$ . 252889)])
#@143 Return an array of [ pins ] for the current instantiation at point.
For example if declare A A (.B(SIG)) then B will be included in the list.
(defalias 'verilog-read-inst-pins #[nil "\212`\303\211\304 \210\305\306\n\307#\203I�\310\303\224\205/�\211\203)�\311\224\225#\266\202\2021�\312\224\225\"\266\202\313 \204\n�C	B\314\315!\203\n�\316\310!\210\202\n�\317	!,\207" [pin pins end-mod-point nil verilog-backward-open-paren re-search-forward "\\.\$[^(,) 	\n\f]*\$\\s-*" t 1 substring-no-properties buffer-substring-no-properties verilog-inside-comment-or-string-p looking-at "(" verilog-forward-sexp-ign-cmt vector] 6 (#$ . 255637)])
#@76 Return an array of [ pins ] for the current argument declaration at point.
(defalias 'verilog-read-arg-pins #[nil "\212`\303\211\304 \210\305\306\n\307#\203?�\310\303\224\205/�\211\203)�\311\224\225#\266\202\2021�\312\224\225\"\266\202\313 \204\n�C	B\202\n�\314	!,\207" [pin pins end-mod-point nil verilog-backward-open-paren re-search-forward "\$[a-zA-Z0-9$_.%`]+\$" t 1 substring-no-properties buffer-substring-no-properties verilog-inside-comment-or-string-p vector] 6 (#$ . 256290)])
#@79 Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT.
(defalias 'verilog-read-auto-constants #[(beg end-mod-point) "\212\304\211\nb\210\305\306\307#\203_�\310\311!\204�\312\313\314 \"\210\315\316\"\210\212\317u\210\320\321!\210\317u\210`)\305\322\307#\203�\321\304\224\205T�\211\203N�\323\224\225#\266\202\202V�\324\224\225\"\266\202\304\211E	B\202/�	+\207" [tpl-end-pt sig-list beg end-mod-point nil re-search-forward "\\<AUTO_CONSTANT" t looking-at "\\s *(" error "%s: Missing () after AUTO_CONSTANT" verilog-point-text search-forward "(" -1 verilog-forward-sexp-cmt 1 "\\s-*\$[\"a-zA-Z0-9$_.%`]+\$\\s-*,*" substring-no-properties buffer-substring-no-properties] 6 (#$ . 256798)])
#@34 True if any AUTO_LISP in buffer.
(defvar verilog-cache-has-lisp nil (#$ . 257528))
(make-variable-buffer-local 'verilog-cache-has-lisp)
#@63 Set `verilog-cache-has-lisp' if any AUTO_LISP in this buffer.
(defalias 'verilog-read-auto-lisp-present #[nil "\212eb\210\301\302\303\304#\211)\207" [verilog-cache-has-lisp re-search-forward "\\<AUTO_LISP(" nil t] 4 (#$ . 257670)])
#@124 Look for and evaluate an AUTO_LISP between START and END.
Must call `verilog-read-auto-lisp-present' before this function.
(defalias 'verilog-read-auto-lisp #[(start end) "\205(�\212	b\210\306\307\n\310#\205'�\311u\210`\312\313!\210`\310\314\f\315#\210+\202�)\207" [verilog-cache-has-lisp start end beg-pt end-pt verilog-in-hooks re-search-forward "\\<AUTO_LISP(" t -1 verilog-forward-sexp-cmt 1 eval-region nil] 4 (#$ . 257910)])
#@228 Recursive routine for parentheses/bracket matching.
EXIT-KEYWD is expression to stop at, nil if top level.
RVALUE is true if at right hand side of equal.
TEMP-NEXT is true to ignore next token, fake from inside case statement.
(defalias 'verilog-read-always-signals-recurse #[(exit-keywd rvalue temp-next) "\306\232\307\211\307\211\307\211<=\307\211>?\307@m\204\232<\204\232\310\311!\2031�\312\313!\210\202\223\310\314!\203G�\312\315!\204\223\316\317\320 `#\210\202\223\310\321!\203`�\322u\210\312\323!\204\223\316\324\320 `#\210\202\223\325`\212\326\307w\327=\203n�\322u\210`)\"\f\307\n\330\232\203\216�\331\332\307\333#\204\221\316\334\320 `#\210\202\221?\203\237�\n\335\232\203\237�\307?\202\221?\203\260�\310\336!\203\260�\333<\202\221\203\326�\n\232\204\306�\337\232\203\326�\n\340\232\203\326�\310\341!\204\326�\333<\nGu\210\202\221\n\342\267\202\307@	A\204\351�\333?\322u\210\202\221\310\343!\203\374�\327\225b\210\202\221\310\344!\203\345u\210\346\337\333\307#\210\202\221\322u\210\202\221\310\341!\203 \322u\210\202T\347\267\2028\307\211@A\202T\202T\202T\202T=\203I\307@	A\307=\202TA\204T\333@\307A\322u\210\202\221=\203l>=>JBL\210\307=A\204\222`Sf\350=\203\207\351B9\"B\3079\202\222\351C9\"C\3079\307@\333A\322u\210\202\221\322u\210\346\352A\307#\210\202\221\322u\210\346\353\333\307#\210\202\221\322u\210
\203\301\307=\354\232\203\334\346\355\307\333#\210\346\355\333\307#\210\346\356\307\211#\210\202\221\346\356\333\307#\210\202\221\357\360!\210\346\361\307\211#\210\307@	A\204\221\333?\202\221\357\360!\210\346\306\333\307#\210\307@	A\204\221\333<\202\221\362\363\n\"\203\216\n\364\235\203,\333@\202\207@\204?\nD\235\204?\362\365\n\"\203E\307@\202\207\366\n!=\203X>=>JBL\210E\203a\367\202kA\203j\370\202k\371>\n?\206x\372\n>J\"?\205\200\n\307\211E=\307E\333\326\307w\210\202\221\322u\210\n\357\373!\210\202�=\205\255>=>JBL\210\307\211=.\n\207" [exit-keywd semi-rvalue keywd last-keywd sig-tolk sig-last-tolk "endcase" nil looking-at "//" search-forward "\n" "/\\*" "*/" error "%s: Unmatched /* */, at char %d" verilog-point-text "(\\*" 1 "*)" "%s: Unmatched (* *), at char %d" buffer-substring-no-properties "a-zA-Z0-9$_.%`" 0 "\"" re-search-forward "[^\\]\"" t "%s: Unmatched quotes, at char %d" "else" "[^ 	\n\f]" "'}" "}" "::" #s(hash-table size 12 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data (";" 220 "'" 239 ":" 276 "=" 346 "?" 414 "[" 427 "(" 439 "begin" 485 "case" 511 "casex" 511 "casez" 511 "randcase" 511)) "'[sS]?[hdxboHDXBO]?[ 	]*[0-9a-fA-F_xzXZ?]+" "'{" 2 verilog-read-always-signals-recurse #s(hash-table size 4 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("endcase" 294 "?" 303 "]" 306 "'}" 309)) 60 append ":" "]" "for" ";" ")" skip-syntax-forward "w_" "end" string-match "^[$`a-zA-Z_]" ("`ifdef" "`ifndef" "`elsif") "^\\$" verilog-symbol-detick-denumber sigs-temp sigs-in sigs-out-unk assoc " " gotend got-sig got-list end-else-check ignore-next rvalue sigs-out-d sigs-out-i verilog-keywords temp-next] 5 (#$ . 258354)])
#@72 Parse always block at point and return list of (outputs inout inputs).
(defalias 'verilog-read-always-signals #[nil "\212\306\211\306\211\306\307\306\211\211#\210\310	\n\"\306	\f\n\f\311\f\n
$.\n\207" [sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in inputs nil verilog-read-always-signals-recurse append vector temps outputs-imm outputs-del] 6 (#$ . 261507)])
#@69 Parse module at point and return list of ( ( file instance ) ... ).
(defalias 'verilog-read-instants #[nil "\306 \210\307 \310\211\212`W\203\210�\311`\312\313\310%\211@\312V\204&�\314	8\203,�\315y\210\202�\316 \210\317\320!\203\202�\315\310\224\205R�\211\203L�\321\224\225#\266\202\202T�\322\224\225\"\266\202\323\310\224\205q�\211\203k�\321\224\225#\266\202\202s�\322\224\225\"\266\202\211
\235\204\201�\fD\nB*\315y\210\202�)\n+\207" [end-mod-point state instants-list instant module verilog-keywords verilog-beg-of-defun-quick verilog-get-end-of-defun nil parse-partial-sexp 0 t 5 1 beginning-of-line looking-at "^\\s-*\$[a-zA-Z0-9`_$]+\$\\s-+\$[a-zA-Z0-9`_$]+\$\\s-*(" substring-no-properties buffer-substring-no-properties 2] 8 (#$ . 261896)])
#@118 With point in middle of an AUTO_TEMPLATE, parse it.
Returns REGEXP and list of ( (signal_name connection_name)... ).
(defalias 'verilog-read-auto-template-middle #[nil "\212\306\307\310\311\211\211\211,\312\313!\203;�\314\311\224\2053�\211\203-�\315\224\225#\266\202\2025�\316\224\225\"\266\202,\310\225b\210\317\320!\210\321\322\323 `\"8\203P�\317\320!\210\202?�-\204Z�.\203\201�\212`/eb\210\317\324/\325#\203p�\fT\202a�`/W\203\200�\314y\210
T\202p�*\212\307u\210\326\314!\210\307u\210`)`	W\203\260\312\327!\203\346�\314\311\224\205\270�\211\203\262�\315\224\225#\266\202\202\272�\316\224\225\"\266\202\330\311\224\205\327�\211\203\321�\315\224\225#\266\202\202\331�\316\224\225\"\266\202\f
FB\310\225b\210\202\217�\312\331!\203Z\321\311\224\205	\211\203\315\224\225#\266\202\202\316\224\225\"\266\202\310\225b\210\332\333\334\311\211\335\314!01234\3105\336405#\203J\3373210$\2110G\310\2243G\\^5\202%0.\340Q\f
F\nB\202\217�\312\341!\203g\310\225b\210\202\217�\312\342!\203w
T\310\225b\210\202\217�\312\343!\203\207\317\342!\210
T\202\217�\312\344!\203\240\330u\210\317\345!\204\217�\346\347\350 `#\210\202\217�\346\351\350 \312\352!\210\335\310!#\210\202\217�\353,\nD\".\207" [rep tpl-end-pt tpl-wild-list tpl-sig-list templateno lineno "\$[0-9]+\$" -1 0 nil looking-at "\\s-*\"\$[^\"]*\$\"" 1 substring-no-properties buffer-substring-no-properties search-forward "(" 3 parse-partial-sexp line-beginning-position "AUTO_TEMPLATE" t verilog-forward-sexp-cmt "\\s-*\\.\$[a-zA-Z0-9`_$]+\$\\s-*(\$.*\$)\\s-*\$,\\|)\\s-*;\$" 2 "\\s-*\\.\$\\([-a-zA-Z0-9`_$+@^.*?|]\\|[][]\\|\\\\[()|0-9]\$+\\)\\s-*(\$.*\$)\\s-*\$,\\|)\\s-*;\$" "^" "@" "\\\$[0-9]+\\\$" match-string string-match replace-match "$" "[ 	\f]+" "\n" "//" "/\\*" "*/" error "%s: Unmatched /* */, at char %d" verilog-point-text "%s: AUTO_TEMPLATE parsing error: %s" ".*$" vector tpl-regexp verilog-auto-inst-template-numbers verilog-auto-template-warn-unused pre-pt string literal fixedcase to-string from-string start] 7 (#$ . 262679)])
#@134 Look for an auto_template for the instantiation of the given MODULE.
If found returns `verilog-read-auto-template-inside' structure.
(defalias 'verilog-read-auto-template #[(module) "\212`\306\307	\310Q\311\312\311\204@�\313
\n#\203@�\212\311\210\314\f\315 \n#)\316\224`X\2039�\316\225`Y\204�\311\211\203�\203I�b\210-\204\236�b\210\306\307	\310Q\311\312\311\204\217�\317
\n#\203\217�\212\320 \210\321\f\322 \n#)\316\224`X\203\210�\316\225`Y\204`�\311\211\203e�\203\230�b\210-\203\247�\316\225b\210\323 \202\253�\324\325\311\"*\207" [pt module noerror bound regexp substr "AUTO_TEMPLATE" "^\\s-*/?\\*?\\s-*" "\\s-+AUTO_TEMPLATE" nil t search-backward re-search-backward line-beginning-position 0 search-forward beginning-of-line re-search-forward line-end-position verilog-read-auto-template-middle vector "" done] 4 (#$ . 264776)])
#@59 Successful lookups with `verilog-read-auto-template-hit'.
(defvar verilog-auto-template-hits nil (#$ . 265657))
(make-variable-buffer-local 'verilog-auto-template-hits)
#@42 Initialize `verilog-read-auto-template'.
(defalias 'verilog-read-auto-template-init #[nil "\205\f�\302\303\304\305\306$\211\207" [verilog-auto-template-warn-unused verilog-auto-template-hits make-hash-table :test equal :rehash-size 4.0] 5 (#$ . 265832)])
#@74 Record that TPL-ASS template from `verilog-read-auto-template' was used.
(defalias 'verilog-read-auto-template-hit #[(tpl-ass) "\205�	\204�\303 \210\304\305\306\n8\307\n8\"\310	#\207" [verilog-auto-template-warn-unused verilog-auto-template-hits tpl-ass verilog-read-auto-template-init puthash vector 2 3 t] 5 (#$ . 266095)])
#@130 Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
Optionally associate it with the specified enumeration ENUMNAME.
(defalias 'verilog-set-define #[(defname defvalue &optional buffer enumname) "r\206�pq\210\306\307	P!\310\n!\311\232\203�\312\202�L\210)\f\205:�\306\313\fP!\314
!\2043�
\315L\210\316\310
!	\"))\207" [buffer defname mac defvalue enumname enumvar intern "vh-" make-local-variable "" "1" "venum-" boundp nil add-to-list] 3 (#$ . 266431)])
#@1932 Read \=`defines and parameters for the current file, or optional FILENAME.
If the filename is provided, `verilog-library-flags' will be used to
resolve it.  If optional RECURSE is non-nil, recurse through \=`includes.

Localparams must be simple assignments to constants, or have their own
"localparam" label rather than a list of localparams.  Thus:

localparam X = 5, Y = 10;	// Ok
    localparam X = {1\='b1, 2\='h2};	// Ok
    localparam X = {1\='b1, 2\='h2}, Y = 10;	// Bad, make into 2 localparam lines

Defines must be simple text substitutions, one on a line, starting
at the beginning of the line.  Any ifdefs or multiline comments around the
define are ignored.

Defines are stored inside Emacs variables using the name
vh-{definename}.

Localparams define what symbols are constants so that AUTOSENSE
will not include them in sensitivity lists.  However any
parameters in the include file are not considered ports in the
including file, thus will not appear in AUTOINSTPARAM lists for a
parent module..

The file variables feature can be used to set defines that
`verilog-mode' can see; put at the *END* of your file something
like:

// Local Variables:
    // vh-macro:"macro_definition"
    // End:

If macros are defined earlier in the same file and you want their values,
you can read them automatically with:

// Local Variables:
    // verilog-auto-read-includes:t
    // End:

Or a more specific alternative example, which requires having
`enable-local-eval' non-nil:

// Local Variables:
    // eval:(verilog-read-defines)
    // eval:(verilog-read-defines "group_standard_includes.v")
    // End:

Note these are only read when the file is first visited, you must use
\[find-alternate-file] RET  to have these take effect after editing them!

If you want to disable the "Process `eval' or hook local variables"
warning message, you need to add to your init file:

(setq enable-local-eval t)
(defalias 'verilog-read-defines #[(&optional filename recurse subcall) "p\212	\204\n�\306 \210\n\203)�\307\n\310 \"\211\203!�\311@!q\210\202(�\312\313\314 \n#\210)\f\203i�eb\210\315\316\317\320#\203i�\321\322\317\224\205V�\211\203P�\323\224\225#\266\202\202X�\324\224\225\"\266\202!\325 \204e�\326
\f\320#\210)\2020�eb\210\315\327\317\320#\203\322\317\224\205\221�\211\203\213�\323\224\225#\266\202\202\223�\324\224\225\"\266\202\330\317\224\205\260�\211\203\252�\323\224\225#\266\202\202\262�\324\224\225\"\266\202%&\325\331\224!\204\332\333\317\211%'()*+\331,\334+',#\203\365�\335*)('$\211'G\331\224*G\\^,\202\320�'.%\336&%#\210*\202l�eb\210\315\337\317\320#\205\240\317-\340\341!\203<\330\317\224\2058\211\2032\323\224\225#\266\202\202:\324\224\225\"\266\202-\342\343!\210\340\344!\203\234\325\331\224!\204\221\336\322\317\224\205k\211\203e\323\224\225#\266\202\202m\324\224\225\"\266\202\330\317\224\205\212\211\203\204\323\224\225#\266\202\202\214\324\224\225\"\266\202-$\210\331\225b\210\342\343!\210\202@)\202\n*\207" [origbuf subcall filename fns recurse inc verilog-getopt-flags verilog-library-filenames buffer-file-name find-file-noselect error "%s: Can't find verilog-read-defines file: %s" verilog-point-text re-search-forward "^\\s-*`include\\s-+\$[^ 	\n\f]+\$" nil t verilog-substitute-include-name 1 substring-no-properties buffer-substring-no-properties verilog-inside-comment-or-string-p verilog-read-defines "^\\s-*`define\\s-+\$[a-zA-Z0-9_$]+\$\\s-+\$.*\$$" 2 0 "\\s-*/[/*].*$" "" string-match replace-match verilog-set-define "^\\s-*\$parameter\\|localparam\$\$\\s-*\\[[^]]*\\]\$?\\s-*" looking-at "[^\n]*\$auto\\|synopsys\$\\s +enum\\s +\$[a-zA-Z0-9_]+\$" forward-comment 99999 "\\s-*,?\\s-*\$?:/[/*].*?$\$?\\s-*\$[a-zA-Z0-9_$]+\$\\s-*=\\s-*\$[^;,]*\$,?\\s-*\$/[/*].*?$\$?\\s-*" defvalue defname string literal fixedcase to-string from-string start enumname] 9 (#$ . 266912)])
#@1207 Read \=`includes for the current file.
This will find all of the \=`includes which are at the beginning of lines,
ignoring any ifdefs or multiline comments around them.
`verilog-read-defines' is then performed on the current and each included
file.

It is often useful put at the *END* of your file something like:

// Local Variables:
    // verilog-auto-read-includes:t
    // End:

Or the equivalent longer version, which requires having
`enable-local-eval' non-nil:

// Local Variables:
    // eval:(verilog-read-defines)
    // eval:(verilog-read-includes)
    // End:

Note includes are only read when the file is first visited, you must use
\[find-alternate-file] RET  to have these take effect after editing them!

It is good to get in the habit of including all needed files in each .v
file that needs it, rather than waiting for compile time.  This will aid
this process, Verilint, and readability.  To prevent defining the same
variable over and over when many modules are compiled together, put a test
around the inside each include file:

foo.v (an include file):
	\=`ifdef _FOO_V	// include if not already included
	\=`else
	\=`define _FOO_V
	... contents of file
	\=`endif // _FOO_V
(defalias 'verilog-read-includes #[nil "\212\301 \210eb\210\302\303\304\305#\205;�\306\307\304\224\205-�\211\203'�\310\224\225#\266\202\202/�\311\224\225\"\266\202!\312\304\305#\210)\202�)\207" [inc verilog-getopt-flags re-search-forward "^\\s-*`include\\s-+\$[^ 	\n\f]+\$" nil t verilog-substitute-include-name 1 substring-no-properties buffer-substring-no-properties verilog-read-defines] 7 (#$ . 270860)])
#@203 Return a simple list of all possible signals in the file.
Bounded by optional region from START to END.  Overly aggressive but fast.
Some macros and such are also found and included.  For dinotrace.el.
(defalias 'verilog-read-signals #[(&optional start end) "\305\211\n\206	�eb\210\206�d\306\307\310#\203\231�\311u\210\312\313!\203)�\314\315!\210\202�\312\316!\2036�\314\317!\210\202�\312\320!\203I�\312\321!\204�\314\322!\210\202�g\323=\203V�\306\324!\210\202�\312\325!\203\223�\326\225b\210\327\305\224\205}�\211\203w�\330\224\225#\266\202\202�\331\224\225\"\266\202\211\f\235\204�	\235\204�	B\202�\327u\210\202�	*\207" [keywd sigs-all start end verilog-keywords nil re-search-forward "[\"/a-zA-Z_.%`]" t -1 looking-at "//" search-forward "\n" "/\\*" "*/" "(\\*" "(\\*\\s-*)" "*)" 34 "[^\\]\"" "\\s-*\$[a-zA-Z0-9$_.%`]+\$" 0 1 substring-no-properties buffer-substring-no-properties] 7 (#$ . 272493)])
#@99 Parse -f, -v etc arguments in ARGLIST list or string.
Use DEFAULT-DIR to anchor paths if non-nil.
(defalias 'verilog-getopt #[(arglist &optional default-dir) "<\204�C\305\211\211\203N�@A\306\307\n\"\203�\310\311\n\224\205>�\211\2038�\312\224\225#\266\202\202@�\313\224\225\"\266\202C\"\314\315\n\"\202�\202�\205;@A\n\316\267\202r�\n\202N�\n\202N�\n\202N�\n\202N�\306\317\n\"\203\230�\314\311\n\"\306\320\n\"\203N�\321\322\314\311\n\"\"\210\314\315\n\"\202~�\202N�\306\323\n\"\204\264�\306\324\n\"\204\264�\306\325\n\"\204\264�\306\326\n\"\203\302�\327\314\311\n\"\314\315\n\"\"\210\202N�\306\330\n\"\204\320�\306\331\n\"\203\335�\321\332\333\314\311\n\"!\"\210\202N�\n\334\232\204N�\306\335\n\"\204N�	\336\267\202)\305\337\340\n\f\"\341\340\n\f\"!\"\210\202N�\305\337\340\n\f\"\305\"\210\202N�\305\321\342\340\n\f\"\"\210\202N�\305\321\332\340\n\f\"\"\210\202N�\306\343\n\"\203N�\321\342\340\n\f\"\"\210\202N�+\207" [arglist next-param arg space-args default-dir nil string-match "^\$[^ 	\n\f]+\$[ 	\n\f]*\$.*$\$" append 1 substring-no-properties buffer-substring-no-properties match-string 2 #s(hash-table size 4 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("-F" 94 "-f" 99 "-v" 104 "-y" 109)) "^\\+libext\\+\$.*\$" "\$[^+]+\$\\+?\$.*\$" verilog-add-list-unique verilog-library-extensions "^-D\$[^+=]*\$[+=]\$.*\$" "^-D\$[^+=]*\$\$\$" "^\\+define\$[^+=]*\$[+=]\$.*\$" "^\\+define\$[^+=]*\$\$\$" verilog-set-define "^\\+incdir\\+\$.*\$" "^-I\$.*\$" verilog-library-directories substitute-in-file-name "+librescan" "^-U\$.*\$" #s(hash-table size 4 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("-F" 240 "-f" 258 "-v" 271 "-y" 284)) verilog-getopt-file verilog-substitute-file-name-path file-name-directory verilog-library-files "^[^-+]"] 8 (#$ . 273430)])
#@95 Read Verilog options from the specified FILENAME.
Use DEFAULT-DIR to anchor paths if non-nil.
(defalias 'verilog-getopt-file #[(filename &optional default-dir) "\212\305\306 \"p\307\211\203�\310@!q\210\202�\311\312\313 #\210eb\210m?\205J�`\314 {\315y\210\316\317	\"\203=�\320	\321\211\224#r\nq\210\322	\f\"\210)\202\"�,\207" [filename line orig-buffer fns default-dir verilog-library-filenames buffer-file-name nil find-file-noselect error "%s: Can't find verilog-getopt-file -f file: %s" verilog-point-text line-end-position 1 string-match "//" substring 0 verilog-getopt] 5 (#$ . 275309)])
#@66 Convert `verilog-library-flags' into standard library variables.
(defalias 'verilog-getopt-flags #[nil "\302\301p\"\203\f�\303\304\305\"\210\306\307\310!\210)\311	!\210\306\307\312!)\207" [verilog-in-hooks verilog-library-flags local-variable-p mapc make-local-variable (verilog-library-extensions verilog-library-directories verilog-library-files verilog-library-flags) t run-hooks verilog-before-getopt-flags-hook verilog-getopt verilog-getopt-flags-hook] 3 (#$ . 275917)])
#@101 Return FILENAME with environment variables substituted.
Use DEFAULT-DIR to anchor paths if non-nil.
(defalias 'verilog-substitute-file-name-path #[(filename default-dir) "\203�\302\303	!\"\207\303	!\207" [default-dir filename expand-file-name substitute-in-file-name] 3 (#$ . 276402)])
#@54 Return FILENAME for include with define substituted.
(defalias 'verilog-substitute-include-name #[(filename) "\306\307\310\211\311\312
	#\203*�\313\f\n	$\211G\311\224\fG\\^\202
�	.\306\307\310\211\314\315\"\311\312
	#\203[�\313\f\n	$\211G\311\224\fG\\^\202>�	.\207" [filename string literal fixedcase to-string from-string "\"" "" nil 0 string-match replace-match verilog-symbol-detick t start] 7 (#$ . 276697)])
#@95 Append to VARREF list the given OBJECT,
unless it is already a member of the variable's list.
(defalias 'verilog-add-list-unique #[(varref object) "	J\235\204�	\302	JC\"L\210	\207" [object varref append] 4 (#$ . 277147)])
#@120 Convert `verilog-library-flags' and similar variables to command line.
Used for __FLAGS__ in `verilog-expand-command'.
(defalias 'verilog-current-flags #[nil "\305\306\307#\211\310\232\203�\311\305\306\n\312#\305\313\310#\305\314\f\310#R	)\207" [verilog-library-flags cmd verilog-library-extensions verilog-library-directories verilog-library-files mapconcat concat " " "" "+libext+" "+" #[(i) "\301\302R\207" [i " -y " " +incdir+"] 4] #[(i) "\301P\207" [i " -v "] 2]] 8 (#$ . 277379)])
#@131 If true, the directory cache is enabled, and file system changes are ignored.
See `verilog-dir-exists-p' and `verilog-dir-files'.
(defvar verilog-dir-cache-preserving nil (#$ . 277881))
#@72 Alist of (((Cwd Dirname) Results)...) for caching `verilog-dir-files'.
(defvar verilog-dir-cache-list nil (#$ . 278073))
#@46 Cached data for `verilog-library-filenames'.
(defvar verilog-dir-cache-lib-filenames nil (#$ . 278200))
#@203 Execute the BODY forms, allowing directory cache preservation within BODY.
This means that changes inside BODY made to the file system will not be
seen by the `verilog-dir-files' and related functions.
(defalias 'verilog-preserve-dir-cache '(macro . #[(&rest body) "\301\302\303BE\207" [body let ((verilog-dir-cache-preserving (current-buffer)) verilog-dir-cache-list verilog-dir-cache-lib-filenames) progn] 4 (#$ . 278311)]))
#@157 Return all filenames in the DIRNAME directory.
Relative paths depend on the `default-directory'.
Results are cached if inside `verilog-preserve-dir-cache'.
(defalias 'verilog-dir-files #[(dirname) "\204�\306\nD\307\f	\"\306\211\f
\203�
A@\202=�\310\n!\311!\2052�\312\306\211\211$\f\f\fD	B\f,\207" [verilog-dir-cache-preserving verilog-dir-cache-list dirname default-directory cache-key fass nil assoc expand-file-name file-directory-p directory-files exp-dirname data] 6 (#$ . 278746)])
#@117 Return true if FILENAME exists.
Like `file-exists-p' but results are cached if inside
`verilog-preserve-dir-cache'.
(defalias 'verilog-dir-file-exists-p #[(filename) "\305!\211\203�	\232\203�\n\202�	\306!\211\205%�\307!\f\235\205%�\310+\207" [filename dirname default-directory dirnamed flist file-name-directory verilog-dir-files file-name-nondirectory t] 3 (#$ . 279260)])
#@120 Return modi if MODULE is specified inside FILENAME, else nil.
Allows version control to check out the file if need be.
(defalias 'verilog-module-inside-filename-p #[(module filename) "\306!\204�\307\310!\205\320�\310!\205\320�\311\211r\312!q\210\212eb\210\313\311\314\311\204N�\315
\f#\203N�\316\317\224!\203F�\315\320\311\314#\210\202)�\317\225\211\203.�,\203\316�\317\311\224\205q�\211\203k�\321\224\225#\266\202\202s�\322\224\225\"\266\202\211\203\316�\323\311\314\311\204\246�\315
\f#\203\246�\316\317\224!\203\236�\315\320\311\314#\210\202\201�\317\225\211\203\206�,\203\316�\324 \232\203 �`	\325	$,\202 �\n,\207" [filename type modi noerror bound regexp file-exists-p fboundp vc-backend nil find-file-noselect "\\<\$module\\|interface\\|program\$\\>" t re-search-forward verilog-inside-comment-or-string-p 0 "[/\"\n]" substring-no-properties buffer-substring-no-properties "[(;]" verilog-read-module-name vector pt module fob name] 6 (#$ . 279652)])
#@39 Return true if SYMBOL is number-like.
(defalias 'verilog-is-number #[(symbol) "\301\302\"\206�\301\303\"\206�\301\304\"\207" [symbol string-match "^[0-9 	:]+$" "^[---]*[0-9]+$" "^[0-9 	]+'s?[hdxbo][0-9a-fA-F_xz? 	]*$"] 3 (#$ . 280672)])
#@186 Return an expanded SYMBOL name without any defines.
If the variable vh-{symbol} is defined, return that value.
If undefined, and WING-IT, return just SYMBOL without the tick, else nil.
(defalias 'verilog-symbol-detick #[(symbol wing-it) "\203?�\303\304\"\203?�\305\306\"\307\310\311P!!\2035�\312\310\311P!!\211\313=\2030�\n\2051�\2021�	)\202:�\n\205:�\211\204�\207" [symbol val wing-it string-match "^`" substring 1 boundp intern "vh-" eval nil] 5 (#$ . 280921)])
#@70 Return SYMBOL with defines converted and any numbers dropped to nil.
(defalias 'verilog-symbol-detick-denumber #[(symbol) "\306\307\"\203F�\310\311\312\211\313\312\"\206�	\203�\314\202�\315\306\n#\203B�\316
\f\n$\211G\315\224
G\\^\202$�\n.\317!?\205N�\207" [symbol verilog-auto-sense-defines-constant string literal fixedcase to-string string-match "^`" "\\[[^0-9: 	]+\\]" "" nil verilog-symbol-detick "0" 0 replace-match verilog-is-number from-string start] 7 (#$ . 281403)])
#@172 Return TEXT without any known defines.
If the variable vh-{symbol} is defined, substitute that value.
This function is intended for use in AUTO_TEMPLATE Lisp expressions.
(defalias 'verilog-symbol-detick-text #[(text) "\304\305\211\n\203<�\306\307\"\203<�\310\311\"\312\313\314	P!!\2036�\315\313\314	P!!\211\2036�\316\305\211$\202�\305\211\204\n�+\207" [val symbol ok text t nil string-match "`\$[a-zA-Z0-9_]+\$" match-string 1 boundp intern "vh-" eval replace-match] 6 (#$ . 281913)])
#@145 Return a list of existing directories given a list of wildcarded DIRNAMES.
Or, just the existing dirnames themselves if there are no wildcards.
(defalias 'verilog-expand-dirnames #[(&optional dirnames) "\204�\306\307!\210\310 \311\216\312!\313\211\211\211\211\211\211\211\211 !\"#$\314\315\"\203 @ A\316\317 \"\203\320\321 \"\320\322 \"\320\323 \"\f#\324\325\313\211#%&'()\326*\316)%*#\203\215�\327('&%$\211%G\326\224(G\\^*\202h�%.#\330\331\313\211#%&'()\326*\316)%*#\203\313�\327('&%$\211%G\326\224(G\\^*\202\246�%.#\332#\333Q#\334
!!!\203-�!@\335
\nQ!\"!A!\316#\n\"\203\335�\n\331\232\204\335�\n\336\232\204\335�\"B\202\335�\337 !\203-� $B$\202-�$.\207" [dirnames save-match-data-internal basefile rest filename root error "`verilog-library-directories' should include at least `.'" match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] reverse nil mapcar substitute-in-file-name string-match "^\$\\|[/\\]*[^*?]*[/\\]\$\$[^/\\]*[*?][^/\\]*\$\$.*\$" match-string 1 2 3 "[*]" ".+" 0 replace-match "[?]" "." "^" "$" verilog-dir-files expand-file-name ".." file-directory-p dirname dirfiles dirfile pattern dirlist string literal fixedcase to-string from-string start] 9 (#$ . 282421) nil])
#@295 Return a search path to find the given FILENAME or module name.
Uses the optional CURRENT filename or variable `buffer-file-name', plus
`verilog-library-directories' and `verilog-library-extensions'
variables to build the path.  With optional CHECK-EXT also check
`verilog-library-extensions'.
(defalias 'verilog-library-filenames #[(filename &optional current check-ext) "\204�\306 	\204
�\307\fE\310
\n\"\307\211\307\211\307\2033�A@\202\225�\311!\211\203\207�\312@\313!\"\f\203P�\202Q�\314\211\203~�\312@P\"\315!\203u�\312\313!\"BA\211\204W�A\211\204=�\237
D\nB.\207" [current verilog-dir-cache-preserving verilog-dir-cache-lib-filenames filename check-ext cache-key buffer-file-name nil assoc verilog-expand-dirnames expand-file-name file-name-directory ("") verilog-dir-file-exists-p fass chkdirs chkdir chkexts fn outlist verilog-library-directories verilog-library-extensions] 5 (#$ . 283751)])
#@197 Return a search path to find the given MODULE name.
Uses the CURRENT filename, `verilog-library-extensions',
`verilog-library-directories' and `verilog-library-files'
variables to build the path.
(defalias 'verilog-module-filenames #[(module current) "\303C\304	\305#\306\307\n\"#\207" [current module verilog-library-files append verilog-library-filenames t mapcar #[(fname) "\302!\203\f�\303	!P\207\207" [fname current file-name-absolute-p file-remote-p] 2]] 6 (#$ . 284729)])
#@89 Non-nil enables caching of signals, etc.  Set to nil for debugging to make things SLOW!
(defvar verilog-cache-enabled t (#$ . 285219))
#@126 Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
For speeding up verilog-modi-get-* commands.
Buffer-local.
(defvar verilog-modi-cache-list nil (#$ . 285361))
(make-variable-buffer-local 'verilog-modi-cache-list)
#@113 Modification tick after which the cache is still considered valid.
Use `verilog-preserve-modi-cache' to set it.
(defvar verilog-modi-cache-preserve-tick nil (#$ . 285598))
#@113 Modification tick after which the cache is still considered valid.
Use `verilog-preserve-modi-cache' to set it.
(defvar verilog-modi-cache-preserve-buffer nil (#$ . 285777))
#@67 Non-nil means allow caching `verilog-modi-current', set by let().
(defvar verilog-modi-cache-current-enable nil (#$ . 285957))
#@64 Currently active `verilog-modi-current', if any, set by let().
(defvar verilog-modi-cache-current nil (#$ . 286090))
#@67 Current endmodule point for `verilog-modi-cache-current', if any.
(defvar verilog-modi-cache-current-max nil (#$ . 286213))
#@79 Return the modi structure for the module currently at point, possibly cached.
(defalias 'verilog-modi-current #[nil "\203�`\211\306H)Y\203�`\nX\203�\207\203W�\307 \212\f\310\211\310\204Q�\311
#\203Q�\312\313\224!\203I�\311\314\310\315#\210\202*�\313\225\211\203/�-\207\307 \207" [verilog-modi-cache-current modi verilog-modi-cache-current-max verilog-modi-cache-current-enable verilog-end-defun-re noerror 2 verilog-modi-current-get nil re-search-forward verilog-inside-comment-or-string-p 0 "[/\"\n]" t bound regexp pt] 5 (#$ . 286343)])
#@62 Return the modi structure for the module currently at point.
(defalias 'verilog-modi-current-get #[nil "\306\211\306\212\306\211\306\n\2044�\307
\f#\2034�\310\311\224!\203-�\307\312\306\313#\210\202�\311\224\211\203�\n,\210\311\306\224\205T�\211\203N�\314\224\225#\266\202\202V�\315\224\225\"\266\202\316\306\211\306\n\204\204�\317
\f#\203\204�\310\311\224!\203}�\317\320\306\313#\210\202`�\311\225\211\203d�\n,\210\321 `)\322 \206\224�p\n	\323\n	$.\207" [name type pt verilog-defun-re noerror bound nil re-search-backward verilog-inside-comment-or-string-p 0 "[/\"]" t substring-no-properties buffer-substring-no-properties "(" re-search-forward "[/\"\n]" verilog-read-module-name buffer-file-name vector regexp fob] 7 (#$ . 286916)])
#@28 Hash of (modulename modi).
(defvar verilog-modi-lookup-cache nil (#$ . 287699))
(make-variable-buffer-local 'verilog-modi-lookup-cache)
#@43 Cache of `current-buffer' at last lookup.
(defvar verilog-modi-lookup-last-current nil (#$ . 287841))
#@55 Cache of `buffer-chars-modified-tick' at last lookup.
(defvar verilog-modi-lookup-last-tick nil (#$ . 287949))
#@197 Find the file and point at which MODULE is defined.
If ALLOW-CACHE is set, check and remember cache of previous lookups.
Return modi if successful, else print message unless IGNORE-ERROR is true.
(defalias 'verilog-modi-lookup #[(module allow-cache &optional ignore-error) "\306 \206�p\307\n\203=�\203=�\f\203=�\310
\n\"\211\203=�\232\203=�\311 \232\2048�	\211\312H)\232\204=�	\210\202\263�\313
\314\" \315 \"\211!\"\307#\"\203p�#\204p�\316 \"@\"\211#\204P�\"A\211\"\204U�##\204\232�$\204\232�\317\320\321 
\211 \232\204\221�\322 \323Q\202\222�\324\325\326!\327#%\210\n\204\245�\330\331\332\333\334$\335
	\n#\210\311 ,	*\207" [current modi verilog-modi-lookup-cache verilog-cache-enabled allow-cache module buffer-file-name nil gethash buffer-chars-modified-tick 1 verilog-symbol-detick t verilog-module-filenames verilog-module-inside-filename-p error "%s: Can't locate `%s' module definition%s\n    Check the verilog-library-directories variable.\n    I looked in (if not listed, doesn't exist):\n	%s" verilog-point-text " (Expanded macro to " ")" "" mapconcat concat "\n	" make-hash-table :test equal :rehash-size 4.0 puthash verilog-modi-lookup-last-current verilog-modi-lookup-last-tick realname orig-filenames filenames mif ignore-error] 10 (#$ . 288067)])
#@63 Filename of MODI, or name of buffer if it's never been saved.
(defalias 'verilog-modi-filename #[(modi) "\301\211\302H)!\203�\303\211\302H)!\206%�\304\211\302H)!\207\211\302H)\207" [modi bufferp 1 buffer-file-name buffer-name] 4 (#$ . 289374)])
#@38 Move point/buffer to specified MODI.
(defalias 'verilog-modi-goto #[(modi) "\204�\302\303!\210\304\211\305H)!\203�\211\305H)\202$�\306\211\305H)!q\210	\307=\204/�\307 \210\211\310H)b\207" [modi major-mode error "Passed unfound modi to goto, check earlier" bufferp 1 find-file-noselect verilog-mode 2] 4 (#$ . 289634)])
#@60 Move point to the file at which a given MODULE is defined.
(defalias 'verilog-goto-defun-file #[(module) "\302\303\"\211\205�\304	!\210\305p!)\207" [module modi verilog-modi-lookup nil verilog-modi-goto switch-to-buffer] 4 (#$ . 289970) "sGoto File for Module: "])
#@129 Run on MODI the given FUNCTION.  Locate the module in a file.
Cache the output of function so next call may have faster access.
(defalias 'verilog-modi-cache-results #[(modi function) "\306\212\307	!\210\310	\nD\"\211\203?�\f\203;�\311 A@\232\2042�
\203;�
A@X\203;�p\232\203;�\312 \3138\232\204?�\306\211\203I�\3148\202\237�\203S�\n \202\215�\315\316\317!\210)deZ\320\321!\205p�\205p�\321\322!\210\315\323\324ed#\210\325\216\315\211\315\306\211\n .	\nD\311 \312 FB)*\207" [fass modi function verilog-modi-cache-list verilog-cache-enabled verilog-modi-cache-preserve-tick nil verilog-modi-goto assoc buffer-chars-modified-tick visited-file-modtime 2 3 t run-hooks verilog-before-save-font-hook boundp font-lock-mode 0 run-hook-with-args before-change-functions #[nil "\303\304ed$\210	\203�\305\306!\210\306\307\310!)\207" [verilog-save-font-mod-hooked fontlocked verilog-in-hooks run-hook-with-args after-change-functions font-lock-mode t run-hooks verilog-after-save-font-hook] 5] verilog-modi-cache-preserve-buffer verilog-save-font-mod-hooked verilog-in-hooks fontlocked inhibit-point-motion-hooks inhibit-modification-hooks verilog-no-change-functions after-change-functions func-returns] 5 (#$ . 290245)])
#@182 Add function return results to the module cache.
Update MODI's cache for given FUNCTION so that the return ELEMENT of that
function now contains the additional SIG-LIST parameters.
(defalias 'verilog-modi-cache-add #[(modi function element sig-list) "\306\212\307	!\210\310	\nD\"\211\205!�\3118\211
\312\f
H\"I)*\207" [fass modi function verilog-modi-cache-list func-returns element nil verilog-modi-goto assoc 3 append sig-list] 7 (#$ . 291506)])
#@380 Execute the BODY forms, allowing cache preservation within BODY.
This means that changes to the buffer will not result in the cache being
flushed.  If the changes affect the modsig state, they must call the
modsig-cache-add-* function, else the results of later calls may be
incorrect.  Without this, changes are assumed to be adding/removing signals
and invalidating the cache.
(defalias 'verilog-preserve-modi-cache '(macro . #[(&rest body) "\301\302\303BE\207" [body let ((verilog-modi-cache-preserve-tick (buffer-chars-modified-tick)) (verilog-modi-cache-preserve-buffer (current-buffer))) progn] 4 (#$ . 291968)]))
#@118 Given a MODI, return the declarations related to the given modport NAME.
Report errors unless optional IGNORE-ERROR.
(defalias 'verilog-modi-modport-lookup-one #[(modi name &optional ignore-error) "\306\307\"\310\n\311\n\312\")\211\313H)\"\211\2042�
\2042�\314\315\316 \211	\232\204/�\317	\320Q\2020�\321$\210\f\3228)\f\211A@)\211\203\317�\323\n@
#\211 \204]�\202\304�\204g� \202\304�\324\325 \326H\326H\"\325 \327H\327H\"\325 \322H\322H\"\325 \330H\330H\"\325 \313H\313H\"\325 \331H\331H\"\325 \332H\332H\"\325 \333H\333H\"\325 \334H\334H\"&	*A\211\204H�,\207" [name realname modi decls modport ignore-error verilog-symbol-detick t assoc verilog-modi-cache-results verilog-read-decls 4 error "%s: Can't locate `%s' modport definition%s" verilog-point-text " (Expanded macro to " ")" "" 2 verilog-modi-modport-lookup-one vector append 0 1 3 5 6 7 8 sig clks b a] 14 (#$ . 292596)])
#@185 Given a MODI, return the declarations related to the given modport NAME-RE.
If the modport points to any clocking blocks, expand the signals to include
those clocking block's signals.
(defalias 'verilog-modi-modport-lookup #[(modi name-re &optional ignore-error) "\306\307\")\211\211\310H)\311\f\312Q\313\211\211\211\211\211\211\211\211\314
&	.	\203\340�\315\f@\211 @)\"\203\331�\n\316@\211 @)!#\"\211#\204p�\"\202\327�\"\204z�#\202\327�\314\317#\320H\"\320H\"\317#\321H\"\321H\"\317#\322H\"\322H\"\317#\323H\"\323H\"\317#\310H\"\310H\"\317#\324H\"\324H\"\317#\325H\"\325H\"\317#\326H\"\326H\"\317#\327H\"\327H\"&	*A\211\204I�\n,\207" [modi mod-decls decls clks name-re interfaces verilog-modi-cache-results verilog-read-decls 4 "^" "$" nil vector string-match verilog-modi-modport-lookup-one append 0 1 2 3 5 6 7 8 gparams consts assigns modports vars in inout out sig ignore-error b a] 14 (#$ . 293545)])
#@56 Return all signals in IN-LIST matching the given ENUM.
(defalias 'verilog-signals-matching-enum #[(in-list enum) "\306	\203�	@\307\n8)\232\203�	@B	A\211\204�\310\311P!\312\f!\205-�\313\f!\211\203O�
@C\211\f\235\203B�\210\202G�\fB)
A\211\2042�*\237)\207" [out-list in-list sig enum enumvar enumlist nil 4 intern "venum-" boundp eval #1=#:x] 4 (#$ . 294532)])
#@70 Return all signals in IN-LIST matching the given REGEXP, if non-nil.
(defalias 'verilog-signals-matching-regexp #[(in-list regexp) "\203\n�\306\232\203\f�	\207\n\307	\203,�\310	@\211@)\"\203%�	@B	A\211\204�\237*\207" [regexp in-list verilog-case-fold out-list case-fold-search sig "" nil string-match] 4 (#$ . 294916)])
#@74 Return all signals in IN-LIST not matching the given REGEXP, if non-nil.
(defalias 'verilog-signals-not-matching-regexp #[(in-list regexp) "\203\n�\306\232\203\f�	\207\n\307	\203,�\310	@\211@)\"\204%�	@B	A\211\204�\237*\207" [regexp in-list verilog-case-fold out-list case-fold-search sig "" nil string-match] 4 (#$ . 295253)])
#@84 Return all signals in IN-LIST matching the given DECL-TYPE and REGEXP,
if non-nil.
(defalias 'verilog-signals-matching-dir-re #[(in-list decl-type regexp) "\203\n�\306\232\203\f�	\207\307\211	\203B�\f\310	@\311
8)\310	@\312
8)	@\211A@)\260\313\n\"\203;�	@B	A\211\204�\237*\207" [regexp in-list to-match out-list decl-type sig "" nil " " 5 7 string-match] 7 (#$ . 295598)])
#@68 Return all signals in IN-LIST with wire/reg data types made blank.
(defalias 'verilog-signals-edit-wire-reg #[(in-list) "\301\302\"\207" [in-list mapcar #[(sig) "\3028)\303\235\203�\304\302\233	\240*\210\207" [sig type 6 ("wire" "reg") nil] 2]] 3 (#$ . 295992)])
#@70 Return all declared signals in DECLS, excluding `assign' statements.
(defalias 'verilog-decls-get-signals #[(decls) "\301\211\302H)\211\303H)\211\304H)\211\305H)\211\306H)\211\307H)&\207" [decls append 0 1 2 3 6 7] 9 (#$ . 296271)])
(defalias 'verilog-decls-get-ports #[(decls) "\301\211\302H)\211\303H)\211\304H)#\207" [decls append 0 1 2] 6])
(defalias 'verilog-decls-get-iovars #[(decls) "\301\211\302H)\211\303H)\211\304H)\211\305H)$\207" [decls append 3 0 1 2] 7])
(defalias 'verilog-modi-cache-add-outputs #[(modi sig-list) "\302\303\304	$\207" [modi sig-list verilog-modi-cache-add verilog-read-decls 0] 5])
(put 'verilog-modi-cache-add-outputs 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-cache-add-inouts #[(modi sig-list) "\302\303\304	$\207" [modi sig-list verilog-modi-cache-add verilog-read-decls 1] 5])
(put 'verilog-modi-cache-add-inouts 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-cache-add-inputs #[(modi sig-list) "\302\303\304	$\207" [modi sig-list verilog-modi-cache-add verilog-read-decls 2] 5])
(put 'verilog-modi-cache-add-inputs 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-cache-add-vars #[(modi sig-list) "\302\303\304	$\207" [modi sig-list verilog-modi-cache-add verilog-read-decls 3] 5])
(put 'verilog-modi-cache-add-vars 'byte-optimizer 'byte-compile-inline-expand)
(defalias 'verilog-modi-cache-add-gparams #[(modi sig-list) "\302\303\304	$\207" [modi sig-list verilog-modi-cache-add verilog-read-decls 7] 5])
(put 'verilog-modi-cache-add-gparams 'byte-optimizer 'byte-compile-inline-expand)
#@85 Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs.
(defalias 'verilog-auto-re-search-do #[(search-for func) "eb\210\306\307\306\f\204.�\310\n	#\203.�\311\312\224!\203'�\310\313\306\307#\210\202�\312\225\211\203�\f,\2059�
 \210\202�\207" [search-for noerror bound regexp pt func nil t re-search-forward verilog-inside-comment-or-string-p 0 "[/\"\n]"] 4 (#$ . 297904)])
#@91 Print out a definition for SIG of the given TYPE,
with appropriate INDENT-PT indentation.
(defalias 'verilog-insert-one-definition #[(sig type indent-pt) "j\210	c\210\n\305\n8)\203�\306\n\305\n8)\261\210\n\307\n8)\203,�\310\n\307\n8)\261\210\n\311\n8)\203`�\310\n\211\311\n8)\205\\�\312\n\311\n8)\203Z�@\fPA\211\204N�\f*)\261\210\n\211A@)\203s�\310\n\211A@)\261\210\313\314\\]j\210hz\315U\204\204�\310c\210\n\211@)c\210\n\316\n8)\205\235�\310\n\316\n8)\261\207" [indent-pt type sig args str 8 "." 5 " " 7 "" 24 16 32 3] 5 (#$ . 298321)])
#@275 Print out a definition for MODI's list of SIGS of the given DIRECTION,
with appropriate INDENT-PT indentation.  If V2K, use Verilog 2001 I/O
format.  Sort unless DONT-SORT.  DIRECTION is normally wire/reg/output.
When MODI is non-null, also add to modi-cache, for tracking.
(defalias 'verilog-insert-definition #[(modi sigs direction indent-pt v2k &optional dont-sort) "\203\234�	\306\267\202\227�\n\307\310\311$*\210\202\234�\n\307\310\311$*\210\202\234�\n\307\310\312$*\210\f\203\234�\n\307\310\311$*\210\202\234�\n\307\310\313$*\210\f\203\234�\n\307\310\311$*\210\202\234�\n\307\310\314$*\210\f\203\234�\n\307\310\311$*\210\202\234�\202\234�\n\307\310\315$*\210\202\234�\316\317	\"\210
\204\247�\320\321\n!\322\"\n\205q\n@#\323#$\324\232\203\341�##\325#8)\203\323�##\325#8)\326\232\203\341�	\327\235\203\335�	\202\324\202##\325#8)\204\362�$\203
	\330\235\205\373�	\331P##\325#8)\206	$P\202\f\203	\332\235\203	\331\fQ\202	%#\210&\203,\333\202-\334c\210'\203N##\313#8)\203N##\313#8)\335\232\203T\336c\210\202j\337%\340\\]j\210\341\342##\313#8)\336#\210\nA)\202\247�\207" [modi direction sigs sig-list verilog-auto-declare-nettype dont-sort #s(hash-table size 7 test equal rehash-size 1.5 rehash-threshold 0.8125 purecopy t data ("wire" 10 "reg" 25 "output" 40 "input" 71 "inout" 102 "interface" 133 "parameter" 136)) verilog-modi-cache-add verilog-read-decls 3 0 2 1 7 error "Unsupported verilog-insert-definition direction: `%s'" sort copy-alist verilog-signals-sort-compare verilog-insert-one-definition "wire" 6 "logic" ("input" "output" "inout") ("input" "output" "inout") " " ("input" "output" "inout") "," ";" "" "\n" 48 40 verilog-insert "// " sig verilog-auto-wire-type indent-pt v2k verilog-auto-wire-comment] 5 (#$ . 298894)])
#@124 Indent to position stored in local `indent-pt' variable, then insert STUFF.
Presumes that any newlines end a list element.
(defalias 'verilog-insert-indent #[(&rest stuff) "\303	\205\"�\203
�\nj\210\304\305	@!\210\306\307	@\"	A\211\204�\304)\207" [need-indent stuff indent-pt t nil verilog-insert string-match "\n$"] 4 (#$ . 300738)])
#@60 Move forward a line, unless at EOB, then insert a newline.
(defalias 'verilog-forward-or-insert-line #[nil "m\203�\300c\207\301y\207" ["\n" nil] 1 (#$ . 301085)])
#@79 Insert comma if previous argument is other than an open parenthesis or endif.
(defalias 'verilog-repair-open-comma #[nil "\212\300 \210\212\301u\210\302\303!)?\205\"�\212\301u\210\304\305x\210\302\306!)?\205\"�\307c)\207" [verilog-backward-syntactic-ws-quick -1 looking-at "[(,]" "a-zA-Z0-9_`" nil "`" ","] 2 (#$ . 301255)])
#@112 If point is at a comma followed by a close parenthesis, fix it.
This repairs those mis-inserted by an AUTOARG.
(defalias 'verilog-repair-close-comma #[nil "\212\300 \210\301u\210\302 \210\301u\210\303\304!\205�\305\306!)\207" [verilog-forward-close-paren -1 verilog-backward-syntactic-ws-quick looking-at "," delete-char 1] 2 (#$ . 301587)])
#@76 Return an expression calculating the length of a range [x:y] in RANGE-EXP.
(defalias 'verilog-make-width-expression #[(range-exp) "\204�\301\207\302\303\"\203�\304\305\"\204�\301\207\302\306\"\2032�\307\310\311\304\305\"!\311\304\312\"!Z!T!\207\302\313\"\203>�\304\305\"\207\302\314\"\203c�\315\304\305\"\316\304\312\"\317\232\203X�\320\202_�\321\304\312\"\316Q\316\260\207\322\207" [range-exp "1" string-match "^\\[\$.*\$\\]$" match-string 1 "^\\s *\$[0-9]+\$\\s *:\\s *\$[0-9]+\$\\s *$" int-to-string abs string-to-number 2 "^\\s *\$[a-zA-Z_][a-zA-Z0-9_]*\$\\s *-\\s *1\\s *:\\s *0\\s *$" "^\$.*\$\\s *:\\s *\$.*\$\\s *$" "(1+(" ")" "0" "" "-(" nil] 7 (#$ . 301936)])
#@75 Return a simplified range expression with constants eliminated from EXPR.
(defalias 'verilog-simplify-range-expression #[(expr) "\203�\306\307	\"\204
�	\207	\310\n\232\204\206\n\232\204�\306\311\"\2030�\312\313\314\211$\202�\306\315\"\203S�\312\316\317\"\320\321\322\316\323\"!!!\316\324\"Q\314\211$\2020�\306\325\"\203\234�\312\316\317\"\316\324\"\326\232\205w�\320\322\316\323\"!\322\316\327\"!\245!\316\324\"\330\232\205\217�\320\322\316\323\"!\322\316\327\"!_!\316\331\"R\314\211$\202S�\306\332\"\203\316\317\"\322\316\323\"!\322\316\327\"!\316\331\"\314%&\211'\333\232\203\313�&[&\316\324\"\333\232\203\334�&%Z\202\341�&%\\\312'\333\232\203\364�\f\334W\203\364�\310\202\366�'\320\f!
Q\314\211$-\202\234�\306\335\"\203�\312\316\317\"\316\324\"\336\232\205+\320\337\322\316\323\"!\340\322\316\327\"!_\"!\316\324\"\341\232\205D\320\337\322\316\323\"!\322\316\327\"!\"!\316\324\"\342\232\205_\320\343\322\316\323\"!\340\322\316\327\"!_\"!\316\324\"\344\232\205x\320\343\322\316\323\"!\322\316\327\"!\"!\316\331\"\260\314\211$\202*\207" [verilog-auto-simplify-expressions expr last-pass out val post string-match "[---+*/<>()]" "" "\$[[({:*/<>+-]\$(\\<\$[0-9A-Za-z_]+\$)\$[])}:*/<>+-]\$" replace-match "\\1\\2\\3" nil "\$[[({:*/<>+-]\$\\$clog2\\s *(\\<\$[0-9]+\$)\$[])}:*/<>+-]\$" match-string 1 int-to-string verilog-clog2 string-to-number 2 3 "\$[[({:*/<>+-]\$\$[0-9]+\$\\s *\$[*/]\$\\s *\$[0-9]+\$\$[])}:*/<>+-]\$" "/" 4 "*" 5 "\$[[({:<>+-]\$\$[0-9]+\$\\s *\$[---+]\$\\s *\$[0-9]+\$\$[])}:<>+-]\$" "-" 0 "\$[[({:]\$\$[0-9]+\$\\s *\$[<]\\{2,3\\}\\|[>]\\{2,3\\}\$\\s *\$[0-9]+\$\$[])}:<>]\$" ">>" lsh -1 "<<" ">>>" ash "<<<" rhs lhs pre] 13 (#$ . 302642)])
#@41 Compute $clog2 - ceiling log2 of VALUE.
(defalias 'verilog-clog2 #[(value) "\301W\203�\302\207\303\304!\304\305!\245!\207" [value 1 0 ceiling log 2] 4 (#$ . 304429)])
#@56 Return true if the VARIABLE-NAME is a type definition.
(defalias 'verilog-typedef-name-p #[(variable-name) "\205�	\306
\307\f\n#,\207" [verilog-typedef-regexp variable-name start string regexp verilog-case-fold nil string-match case-fold-search] 4 (#$ . 304605)])
#@74 Delete autos that occupy multiple lines, between begin and end comments.
(defalias 'verilog-delete-autos-lined #[nil "\301y\210`\302\303!\205�\304\305\306\307#\205�\306\210\301y\210`|)\207" [pt 1 looking-at "\\s-*// Beginning" search-forward "// End of automatic" nil t] 4 (#$ . 304884)])
#@48 Delete begin/end auto pair at point, if empty.
(defalias 'verilog-delete-empty-auto-pair #[nil "\300y\210\301\302!\205�`\212\303y\210`)|\207" [0 looking-at "\\s-*// Beginning of automatic.*\n\\s-*// End of automatics\n" 2] 2 (#$ . 305184)])
#@116 Find the close parenthesis that match the current point.
Ignore other close parenthesis with matching open parens.
(defalias 'verilog-forward-close-paren #[nil "\305\306V\205X�\307\310\311\310\f\2043�\312\n	#\2033�\313\306\224!\203,�\312\314\310\311#\210\202�\306\225\211\203�\f,\204>�\315\316\317 \"\210h\320U\203K�T\211\202�h\321U\203�S\211\202�)\207" [parens noerror bound regexp pt 1 0 "[()]" nil t re-search-forward verilog-inside-comment-or-string-p "[/\"\n]" error "%s: Mismatching ()" verilog-point-text 40 41] 5 (#$ . 305433)])
#@115 Find the open parenthesis that match the current point.
Ignore other open parenthesis with matching close parens.
(defalias 'verilog-backward-open-paren #[nil "\305\306V\205X�\307\310\311\310\f\2043�\312\n	#\2033�\313\306\224!\203,�\312\314\310\311#\210\202�\306\224\211\203�\f,\204>�\315\316\317 \"\210g\320U\203K�T\211\202�g\321U\203�S\211\202�)\207" [parens noerror bound regexp pt 1 0 "[()]" nil t re-search-backward verilog-inside-comment-or-string-p "[/\"]" error "%s: Mismatching ()" verilog-point-text 41 40] 5 (#$ . 305994)])
#@108 Find the open bracket that match the current point.
Ignore other open bracket with matching close bracket.
(defalias 'verilog-backward-open-bracket #[nil "\305\306V\205X�\307\310\311\310\f\2043�\312\n	#\2033�\313\306\224!\203,�\312\314\310\311#\210\202�\306\224\211\203�\f,\204>�\315\316\317 \"\210g\320U\203K�T\211\202�g\321U\203�S\211\202�)\207" [parens noerror bound regexp pt 1 0 "[][]" nil t re-search-backward verilog-inside-comment-or-string-p "[/\"]" error "%s: Mismatching []" verilog-point-text 93 91] 5 (#$ . 306553)])
#@121 Delete the automatic inst/sense/arg created by autos.
Deletion stops at the matching end parenthesis, outside comments.
(defalias 'verilog-delete-to-paren #[nil "`\212\300 \210\301\302!\210\303u\210`)|\207" [verilog-backward-open-paren verilog-forward-sexp-ign-cmt 1 -1] 3 (#$ . 307107)])
#@110 Return if a .* AUTOINST is safe to delete or expand.
It was created by the AUTOS themselves, or by the user.
(defalias 'verilog-auto-star-safe #[nil "\205\n�\302\303	\304Q!\207" [verilog-auto-star-expand verilog-inst-comment-re looking-at "[ 	\n\f,]*\$[)]\\|// " "\$"] 4 (#$ . 307403)])
#@38 Delete a .* AUTOINST, if it is safe.
(defalias 'verilog-delete-auto-star-all #[nil "\300 \205�\301 \207" [verilog-auto-star-safe verilog-delete-to-paren] 1 (#$ . 307699)])
#@208 Delete all .* implicit connections created by `verilog-auto-star'.
This function will be called automatically at save unless
`verilog-auto-star-save' is set, any non-templated expanded pins will be
removed.
(defalias 'verilog-delete-auto-star-implicit #[nil "\305\211\211\212eb\210\306\307\305\310#\205s�`\311 \210\212\312\313\n\310#\205$�\314 \310)`\nT|\210\203\n�\212\315y\210\316\317\320Q!\203E�\321\224\321\225|\210\2020�)`\212\315u\210\316\322!\204I�\316\323!\203]�`T\f|\210*n\203e�	j\210\324c\210\325\323!\210\326\327!\210\202\n�,\207" [have-close-paren indent paren-pt verilog-inst-comment-re rtn-pt nil re-search-forward "// Implicit \\.\\*" t beginning-of-line search-forward ");" current-indentation -1 looking-at "\\s *//\\s *" "\n" 0 "[ 	\n\f]" "," ");\n" re-search-backward delete-char 1] 4 (#$ . 307879) nil])
#@136 Perform `verilog-delete-auto' on the current buffer.
Intended for internal use inside a `verilog-save-font-no-change-functions' block.
(defalias 'verilog-delete-auto-buffer #[nil "\301\302\303!\210)\304\305\306\"\210\304\307\310\"\210\304\311\312\"\210eb\210\313\314\315\301#\203(�\316\317!\210\202�\301\302\320!)\207" [verilog-in-hooks t run-hooks verilog-before-delete-auto-hook verilog-auto-re-search-do "/\\*AUTO[A-Za-z0-9_]+\$\\|([^)]*)\\|(\"[^\"]*\")\$.*?\\*/" verilog-delete-autos-lined "/\\*\\<\$A\\(?:S\\|UTO\\(?:ARG\\|CONCATWIDTH\\|INST\\(?:PARAM\$?\\|SENSE\\)\\)\\)\\>\$(.*?)\$?\\*/" verilog-delete-to-paren "\\.\\*" verilog-delete-auto-star-all re-search-forward "\\s-*// \$Templated\\|Implicit \\.\\*\$\$[ 	LT0-9]*\\| LHS: .*\$$" nil replace-match "" verilog-delete-auto-hook] 4 (#$ . 308719)])
#@260 Delete the automatic outputs, regs, and wires created by \[verilog-auto].
Use \[verilog-auto] to re-insert the updated AUTOs.

The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
called before and after this function, respectively.
(defalias 'verilog-delete-auto #[nil "\212\306 \203�\307\306 !\210\203�\310 \204�\311p\312 )\202]�\313\314\315!\210)deZ\316\304!\2058�\f\2058�\304\317!\210\313\320\321ed#\210\322\216\313\211\313\311\211\310 \204W�\311p\312 .	)\207" [verilog-save-font-mod-hooked verilog-scan-cache-tick verilog-scan-cache-preserving verilog-in-hooks font-lock-mode fontlocked buffer-file-name find-file-noselect verilog-scan-cache-ok-p nil verilog-delete-auto-buffer t run-hooks verilog-before-save-font-hook boundp 0 run-hook-with-args before-change-functions #[nil "\303\304ed$\210	\203�\305\306!\210\306\307\310!)\207" [verilog-save-font-mod-hooked fontlocked verilog-in-hooks run-hook-with-args after-change-functions font-lock-mode t run-hooks verilog-after-save-font-hook] 5] inhibit-point-motion-hooks inhibit-modification-hooks verilog-no-change-functions after-change-functions] 5 (#$ . 309547) nil])
#@1111 Examine legacy non-AUTO code and insert AUTOs in appropriate places.

Any always @ blocks with sensitivity lists that match computed lists will
be replaced with /*AS*/ comments.

Any cells will get /*AUTOINST*/ added to the end of the pin list.
Pins with have identical names will be deleted.

Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
support adding new ports.  You may wish to delete older ports yourself.

For example:

module ExampInject (i, o);
          input i;
          input j;
          output o;
          always @ (i or j)
             o = i | j;
          InstModule instName
            (.foobar(baz),
             .j(j));
        endmodule

Typing \[verilog-inject-auto] (with an appropriate submodule not
shown) will make this into:

module ExampInject (i, o/*AUTOARG*/
          // Inputs
          j);
          input i;
          output o;
          always @ (/*AS*/i or j)
             o = i | j;
          InstModule instName
            (.foobar(baz),
             /*AUTOINST*/
             // Outputs
             j(j));
        endmodule
(defalias 'verilog-inject-auto #[nil "\300\301!\207" [verilog-auto t] 2 (#$ . 310731) nil])
#@59 Inject AUTOARG into new code.  See `verilog-inject-auto'.
(defalias 'verilog-inject-arg #[nil "\212eb\210\305\306\307\306\204/�\310\n	#\203/�\311\312\224!\203(�\310\313\306\307#\210\202\f�\312\225\211\203�,\205\263�\212\314\306\307\306\204`�\310\n	#\203`�\311\312\224!\203Y�\310\313\306\307#\210\202=�\312\225\211\203A�,\210`)\310\315\f\307#\204\257�\316\306\307\306\204\231�\310\n	#\203\231�\311\312\224!\203\222�\310\313\306\307#\210\202v�\312\225\211\203z�,\210\317u\210\320 \210\317u\210\321\322!\203\257�\323\324!\210)\202�)\207" [noerror bound regexp pt endmodp "\\<module\\>" nil t re-search-forward verilog-inside-comment-or-string-p 0 "[/\"\n]" "\\<endmodule\\>" "/\\*AUTOARG\\*/" ";" -1 verilog-backward-syntactic-ws-quick looking-at ")" verilog-insert "/*AUTOARG*/"] 4 (#$ . 311939)])
#@61 Inject AUTOSENSE into new code.  See `verilog-inject-auto'.
(defalias 'verilog-inject-sense #[nil "\212eb\210\306\307\310\307\204/�\311\n	#\203/�\312\313\224!\203(�\311\314\307\310#\210\202\f�\313\225\211\203�,\205\257�`\315 \211\316
\317\")\307\211\320u\210\321\322!\210\320u\210\323\f\310\307\204}�\324\n	#\203}�\312\313\224!\203v�\324\325\307\310#\210\202Z�\313\224\211\203^�,\204\253�\326\327\f`\"!\330\307\"\331\"\204\253�\331\"\204\253�\f`|\210\332\333!\210-\202�)\207" [noerror bound regexp pt start-pt modi "\\<always\\s *@\\s *(" nil t re-search-forward verilog-inside-comment-or-string-p 0 "[/\"\n]" verilog-modi-current verilog-modi-cache-results verilog-read-decls -1 verilog-forward-sexp-ign-cmt 1 "/\\*\$AUTOSENSE\\|AS\$\\*/" re-search-backward "[/\"]" verilog-signals-from-signame verilog-read-signals verilog-auto-sense-sigs verilog-signals-not-in verilog-insert "/*AS*/" moddecls pre-sigs got-sigs] 5 (#$ . 312768)])
#@60 Inject AUTOINST into new code.  See `verilog-inject-auto'.
(defalias 'verilog-inject-inst #[nil "\212eb\210\306\307\310\307\204/�\311\n	#\203/�\312\313\224!\203(�\311\314\307\310#\210\202\f�\313\225\211\203�,\205
\315 \210h\316U\203F�\317u\210\320 \210\202�\317u\210i\313\\\212\320 \210`)\321\f\310\307\204�\311\n	#\203�\312\313\224!\203x�\311\314\307\310#\210\202\\�\313\225\211\203`�,\203\212�\fb\210\202	\307\322\f\310\307\204\270�\311\n	#\203\270�\312\313\224!\203\261�\311\314\307\310#\210\202\225�\313\225\211\203\231�,\203\350�\313\224\313\225|\210\f\313\225\313\224ZZ\323\324!\204\327�\323\325!\203\215�\313\224\313\225|\210\f\313\225\313\224ZZ\202\313�)\320 \210\326u\210\327\330`S\310#\203\313\224\313\225|\210\202\357�\331\332!\210\333\334!\210*\202�)\207" [noerror bound regexp pt end-pt indent-pt "\\.\\s *[a-zA-Z0-9`_$]+\\s *(\\s *[a-zA-Z0-9`_$]+\\s *)" nil t re-search-forward verilog-inside-comment-or-string-p 0 "[/\"\n]" verilog-backward-open-paren 35 1 verilog-forward-close-paren "\$/\\*AUTOINST\\((.*?)\$?\\*/\\|\\.\\*\\)" "\\.\\s *\$[a-zA-Z0-9`_$]+\$\\s *(\\s *\\1\\s *)\\s *" looking-at "[ 	\n\f,]+" "//[^\n]*" -1 re-search-backward "[ 	\n\f]+" verilog-insert "\n" verilog-insert-indent "/*AUTOINST*/" case-fold-search] 4 (#$ . 313751)])
#@201 Return nil if buffers B1 and B2 have same contents.
Else, return point in B1 that first mismatches.
If optional WHITESPACE true, ignore whitespace.
If optional REGEXP, ignore differences matching it.
(defalias 'verilog-diff-buffers-p #[(b1 b2 &optional whitespace regexp) "\212\306r	q\210eb)rq\210eb)r	q\210d)rq\210d)
\307\211\306\211\n=\203<�\f=\204\306�\203]�r	q\210\nb\210\310\306w\210`)rq\210\fb\210\310\306w\210`)\203\206�r	q\210\nb\210\311!\203s�\312\225)rq\210\fb\210\311!\203\205�\312\225)
\nZ
\fZ^\313\f\f\\	\n\n\\&\211\312U\203\254�\202\261�\314!S\n\f\n\\\f\\\202.�\n
=\205\320�\f
=?\205\325�\n.\n\207" [case-fold-search b1 p1 b2 p2 maxp1 nil -1 " 	\n
\f" looking-at 0 compare-buffer-substrings abs maxp2 op1 op2 progress size whitespace regexp] 9 (#$ . 315062)])
#@258 View the differences between file F1 and buffer B2.
This requires the external program `diff-command' to be in your `exec-path',
and uses `diff-switches' in which you may want to have "-u" flag.
Ignores WHITESPACE if t, and writes output to stdout if SHOW.
(defalias 'verilog-diff-file-with-buffer #[(f1 b2 &optional whitespace show) "\306!\204
�\307\310\311	!\"\207\312\313!r\nq\210\314\216p\315\316!\317\216r	q\210\214~\210\320ed\321\322%\210*\323
\321\f\324\203?�\325\202@�\326&\210\203U�r\fq\210\307\327\330 \"\210))\331\332!\210\306!\205c�\333!-\207" [f1 b2 #1=#:temp-buffer f2 outbuf diff-command file-exists-p message "Buffer `%s' has no associated file on disk" buffer-name generate-new-buffer " *temp*" #[nil "\301!\205	�\302!\207" [#1# buffer-name kill-buffer] 2] make-temp-file "vm-diff-auto-" #[nil "\300\207" [nil] 1] write-region nil nomessage call-process t "-b" "" "%s" buffer-string sit-for 0 delete-file diff-switches whitespace show] 9 (#$ . 315905)])
#@178 Report differences detected with `verilog-diff-auto'.
Differences are between buffers B1 and B2, starting at point
DIFFPT.  This function is called via `verilog-diff-function'.
(defalias 'verilog-diff-report #[(b1 b2 diffpt) "rq\210\305 )\306\307	rq\210\310e\n\")#\210\203#�\311	\f\312\211$\202'�\313\f\")\207" [b1 name1 diffpt noninteractive b2 buffer-file-name verilog-warn-error "%s:%d: Difference in AUTO expansion found" count-lines verilog-diff-file-with-buffer t ediff-buffers] 6 (#$ . 316901)])
#@448 Expand AUTOs in a temporary buffer and indicate any change.
Whitespace is ignored when detecting differences, but once a
difference is detected, whitespace differences may be shown.

To call this from the command line, see \[verilog-batch-diff-auto].

The action on differences is selected with
`verilog-diff-function'.  The default is `verilog-diff-report'
which will report an error and run `ediff' in interactive mode,
or `diff' in batch mode.
(defalias 'verilog-diff-auto #[nil "p\306\211\305 \307\212\310!\203�\311!\210\306\312!)rq\210	\313\216r\fq\210\306)\314 \210\315 \210+\316\f\317$\211\204O�\204H�\320\321!\210\311!\210\202V�\f\n#\210\n.\207" [newname name1 diffpt b2 b1 buffer-file-name nil "*Verilog-Diff*" get-buffer kill-buffer clone-buffer #[nil "rq\210	\211)\207" [b1 name1 buffer-file-name] 2] verilog-auto verilog-star-cleanup verilog-diff-buffers-p t message "AUTO expansion identical" verilog-diff-ignore-regexp noninteractive verilog-diff-function] 6 (#$ . 317416) nil])
#@43 On saving or diff, cleanup .* expansions.
(defalias 'verilog-star-cleanup #[nil "?\205�\301 \207" [verilog-auto-star-save verilog-delete-auto-star-implicit] 1 (#$ . 318442)])
#@39 On saving see if we need auto update.
(defalias 'verilog-auto-save-check #[nil "\203L�\212\304 \305\216\306eb\210\307\310\306\311#,\203L�\312=\203$�\313 \210\202L�\314 \203L�\315 =\204L�\316=\203<�\313 \210\202L�\317\320!\203E�\313 \210\321\303!\210\315 \322 \210\306\207" [verilog-auto-save-policy save-match-data-internal case-fold-search verilog-auto-update-tick match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] nil re-search-forward "AUTO" t force verilog-auto buffer-modified-p buffer-chars-modified-tick detect yes-or-no-p "AUTO statements not recomputed, do it now? " make-local-variable verilog-star-cleanup] 4 (#$ . 318625)])
#@55 Return file local variable segment at bottom of file.
(defalias 'verilog-auto-read-locals #[nil "\212db\210\300\301\302\303#\203�\304`d\"\202�\305)\207" [re-search-backward "Local Variables:" nil t buffer-substring-no-properties ""] 4 (#$ . 319314)])
#@99 Read file local variable segment at bottom of file if it has changed.
If FORCE, always reread it.
(defalias 'verilog-auto-reeval-locals #[(&optional force) "\303 	\204�\n\232?\205�\304\302!\210\305 \210\306)\207" [curlocal force verilog-auto-last-file-locals verilog-auto-read-locals make-local-variable hack-local-variables t] 2 (#$ . 319573)])
#@106 Print a list of ports for AUTOARG.
Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT.
(defalias 'verilog-auto-arg-ports #[(sigs message indent-pt) "\205k�	\203�\306\307!\310\"\311c\210\nj\210c\210\311c\210\312\nj\210\205j�
\313=\2035�\fc\210\nj\210\311\202W�\314\315i@\211@)G#V\203R�\311c\210\nj\210\316\202W�\fc\210\316@\211@)\317\261\210A\211\204$�\320)\207" [sigs verilog-auto-arg-sort indent-pt message space verilog-auto-arg-format sort copy-alist verilog-signals-sort-compare "\n" "" single + 2 " " "," nil sig fill-column] 5 (#$ . 319932)])
#@1475 Expand AUTOARG statements.
Replace the argument declarations at the beginning of the
module with ones automatically derived from input and output
statements.  This can be dangerous if the module is instantiated
using position-based connections, so use only name-based when
instantiating the resulting module.  Long lines are split based
on the `fill-column', see \[set-fill-column].

Limitations:
  Concatenation and outputting partial buses is not supported.

Typedefs must match `verilog-typedef-regexp', which is disabled by default.

For example:

module ExampArg (/*AUTOARG*/);
          input i;
          output o;
        endmodule

Typing \[verilog-auto] will make this into:

module ExampArg (/*AUTOARG*/
          // Outputs
          o,
          // Inputs
          i);
          input i;
          output o;
        endmodule

The argument declarations may be printed in declaration order to
best suit order based instantiations, or alphabetically, based on
the `verilog-auto-arg-sort' variable.

Formatting is controlled with `verilog-auto-arg-format' variable.

Any ports declared between the ( and /*AUTOARG*/ are presumed to be
predeclared and are not redeclared by AUTOARG.  AUTOARG will make a
conservative guess on adding a comma for the first signal, if you have
any ifdefs or complicated expressions before the AUTOARG you will need
to choose the comma yourself.

Avoid declaring ports manually, as it makes code harder to maintain.
(defalias 'verilog-auto-arg #[nil "\212\305 \211\306\307\")\310 \311H\312 \210\313\314	\211\311H)\n\"\315\f#\210\313\314	\211\316H)\n\"\317\f#\210\313\314	\211\320H)\n\"\321\f#\210\322 \210`Sf\323=\204L�\324c\210\fj,\207" [modi moddecls skip-pins decls verilog-indent-level-declaration verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-read-arg-pins 0 verilog-repair-open-comma verilog-auto-arg-ports verilog-signals-not-in "// Outputs" 1 "// Inouts" 2 "// Inputs" verilog-repair-close-comma 47 "\n"] 5 (#$ . 320528)])
#@995 Expand AUTOASSIGNMODPORT statements, as part of \[verilog-auto].
Take input/output/inout statements from the specified interface
and modport and use to build assignments into the modport, for
making verification modules that connect to UVM interfaces.

The first parameter is the name of an interface.

The second parameter is a regexp of modports to read from in
  that interface.

The third parameter is the instance name to use to dot reference into.

The optional fourth parameter is a regular expression, and only
  signals matching the regular expression will be included.

Limitations:

Interface names must be resolvable to filenames.  See `verilog-auto-inst'.

Inouts are not supported, as assignments must be unidirectional.

If a signal is part of the interface header and in both a
  modport and the interface itself, it will not be listed.  (As
  this would result in a syntax error when the connections are
  made.)

See the example in `verilog-auto-inout-modport'.
(defalias 'verilog-auto-assign-modport #[nil "\212\306\307\310\"\211@A@\3118\3078\312\211%\313	\314\"\211%\205\315 &%'\316'\317\")(\320%\n\")\321(\211*\307H)\322)\211*\311H)\323(!\"\"+\321(\211*\307H)\322)\211*\324H)\323(!\"\",\325y\210\326\327\330+\f\"\331
#!+\326\327\330,\f\"\332
#!,\333\334+!\335\"+\333\334,!\335\",+\204\250�,\205\336\337!\210,\211-\203\326�\336\340-@\211.@)\341\342-@\211.@)\343&\210-A\211-\204\264�)+\211-\203\336\340\342-@\211.@)\341-@\211.@)\343&\210-A\211-\204\337�)\336\344!-.\207" [params submod modport-re inst-name regexp direction-re verilog-read-auto-params 3 4 2 nil verilog-modi-lookup t current-indentation verilog-modi-cache-results verilog-read-decls verilog-modi-modport-lookup verilog-signals-in verilog-signals-not-in verilog-decls-get-ports 0 1 verilog-signals-edit-wire-reg verilog-signals-matching-dir-re verilog-signals-matching-regexp "input" "output" sort copy-alist verilog-signals-sort-compare verilog-insert-indent "// Beginning of automatic assignments from modport\n" "assign " " = " "." ";\n" "// End of automatics\n" submodi indent-pt modi submoddecls submodportdecls decls sig-list-i sig-list-o sigs sig] 9 (#$ . 322561)])
(defalias 'verilog-auto-inst-port-map #[(_port-st) "\300\207" [nil] 1])
#@26 See `verilog-auto-inst'.
(defvar vl-cell-type nil (#$ . 324878))
#@26 See `verilog-auto-inst'.
(defvar vl-cell-name nil (#$ . 324949))
#@26 See `verilog-auto-inst'.
(defvar vl-modport nil (#$ . 325020))
#@26 See `verilog-auto-inst'.
(defvar vl-name nil (#$ . 325089))
#@26 See `verilog-auto-inst'.
(defvar vl-width nil (#$ . 325155))
#@26 See `verilog-auto-inst'.
(defvar vl-dir nil (#$ . 325222))
#@26 See `verilog-auto-inst'.
(defvar vl-bits nil (#$ . 325287))
#@26 See `verilog-auto-inst'.
(defvar vl-mbits nil (#$ . 325353))
#@319 Print out an instantiation connection for this PORT-ST.
Insert to INDENT-PT, use template TPL-LIST.
@ are instantiation numbers, replaced with TPL-NUM.
@"(expression @)" are evaluated, with @ as a variable.
If FOR-STAR add comment it is a .* expansion.
If PAR-VALUES replace final strings with these parameter values.
(defalias 'verilog-auto-inst-port #[(port-st indent-pt moddecls tpl-list tpl-num for-star par-values) "\211@)\306\n@\"\206�\307!\211@)\310	\211A@)!)>\311	8)?\312	8)@\313	8)\203q�\211\313	8)\205m�\314	\313	8)ABA\203j�A@BPBAA\211A\204Y�B*)\202r�\314CD\315=\204\253�D\316=\203\213�\317	8)\203\253�\306\n\320E!\"\203\253�\211A@)\306\n\320E!\"\211A@)\232\204\270�\211A@)\206\271�\314\202\271�\314F\321GHI\321\211JKI\203\345F\314\232\204\345I\203\310\322I@@\323Q\324I@A@\325Q\315\211FLMNOP\326Q\327PLQ#\203\330ONML$\211LG\326\224OG\\^Q\202\371�L.F\322I@@\323Q\324I@A@\325Q\315\211CLMNOP\326Q\327PLQ#\203i\330ONML$\211LG\326\224OG\\^Q\202DL.C@\205\275\322I@@\323Q\324I@A@\325Q\315\211@LMNOP\326Q\327PLQ#\203\271\330ONML$\211LG\326\224OG\\^Q\202\224L.@IA\211I\204\331�\331F!F\331C!C@\205\335\331@!@\310F!>\211A@)\203\367\313	8)\204�\312	8)\203 \332CF@\203\333\202\314@\203@\202\314\334\260\202$F\260K\n?\203M\306\nE\211R\311H)\"\211\205B	\311	8))\204M\333?P\202N\314KQJ\f\203_\fA@J\202\222A@\203\222A@\211S\203\221\327S@@\n\"\203\210S@\330S@A@\315\321\n$JSA\211S\204n)\f\203\327\335J\"\203]\327\336J\"\203]\337J\326\211\224#\340 T\341\216\342\343J\"U\344\345\321\211ULMNOP\326Q\327PLQ#\203\362\330ONML$\211LG\326\224OG\\^Q\202\315L.U\346V\321\211ULMNOP\326Q\327PLQ#\2031\330ONML$\211LG\326\224OG\\^Q\202\fL.U\347\350\351U!@!\352\"\211W\247\203N\353W!WW,\337J\326\225\"QJ\202\236\346V\321\211JLMNOP\326Q\327PLQ#\203\226\330ONML$\211LG\326\224OG\\^Q\202qL.J\354K\321\211JLMNOP\326Q\327PLQ#\203\325\330ONML$\211LG\326\224OG\\^Q\202\260L.J\355F\321\211JLMNOP\326Q\327PLQ#\203\330ONML$\211LG\326\224OG\\^Q\202\357L.JXj\210\333\n\261\210Y\203/\nJ\232\204:Zj\210\324J\325\261\210\356c\210\f\203\206\357\f!\210Z\360W\203P\361\202Q\362Z\\j\210[\363=\203g\364\365\366\f@\367$\202\244[\203\200\364\365\370\371\372\f8!\373\371\312\f8!\367&\202\244\364\374!\202\244\\\203\242Z\360W\203\226\361\202\227\362Z\\j\210\364\375!\202\244\367c.\f\207" [port-st sig port tpl-list tpl-ass vl-name assoc verilog-auto-inst-port-map verilog-make-width-expression 8 3 7 "" t unsigned 5 verilog-decls-get-signals nil "\\<" "\\>" "(" ")" 0 string-match replace-match verilog-simplify-range-expression "/*" "." "*/" "@\".*[^\\]\"" "@\"\$\\([^\\\"]\\|\\\\.\$*\\)\"" substring match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] match-string 1 "\\\\\"" "\"" "@" prin1 eval read-from-string #[(_ch) "\300\207" [nil] 1] number-to-string "\\[\\]\\[\\]" "\\[\\]" "," verilog-read-auto-template-hit 48 24 16 lhs verilog-insert " // Templated" " LHS: " "\n" " T" int-to-string 2 " L" " // Templated\n" " // Implicit .*\n" vl-width vl-modport vl-memory args str vl-mbits verilog-auto-inst-vector moddecls vl-bits case-fold-search par-values check-values tpl-net dflt-bits string literal fixedcase to-string from-string start decls wildcards save-match-data-internal expr tpl-num value indent-pt verilog-auto-inst-dot-name verilog-auto-inst-column verilog-auto-inst-template-numbers for-star] 9 (#$ . 325421)])
#@79 For `verilog-auto-inst' print a list of ports using `verilog-auto-inst-port'.
(defalias 'verilog-auto-inst-port-list #[(sig-list indent-pt moddecls tpl-list tpl-num for-star par-values) "\203�\302\303	!\304\"\305\306	\"\207" [verilog-auto-inst-sort sig-list sort copy-alist verilog-signals-sort-compare mapc #[(port) "\306	\n\f
&\207" [port indent-pt moddecls tpl-list tpl-num for-star verilog-auto-inst-port par-values] 8]] 3 (#$ . 329112)])
#@87 Insert , etc before first ever port in this instant, as part of \[verilog-auto-inst].
(defalias 'verilog-auto-inst-first #[nil "\304c\210\212\305\306\211\306\204/�\307\n	#\203/�\310\311\224!\203(�\307\312\306\313#\210\202\f�\311\224\211\203�,\210\314\315!\205=�\316u\210\317c)\207" [noerror bound regexp pt "\n" "[^ 	\n\f]" nil re-search-backward verilog-inside-comment-or-string-p 0 "[/\"]" t looking-at ")\\|\\*" 1 ","] 4 (#$ . 329569)])
#@758 Expand SystemVerilog .* pins, as part of \[verilog-auto].

If `verilog-auto-star-expand' is set, .* pins are treated if they were
AUTOINST statements, otherwise they are ignored.  For safety, Verilog mode
will also ignore any .* that are not last in your pin list (this prevents
it from deleting pins following the .* when it expands the AUTOINST.)

On writing your file, unless `verilog-auto-star-save' is set, any
non-templated expanded pins will be removed.  You may do this at any time
with \[verilog-delete-auto-star-implicit].

If you are converting a module to use .* for the first time, you may wish
to use \[verilog-inject-auto] and then replace the created AUTOINST with .*.

See `verilog-auto-inst' for examples, templates, and more information.
(defalias 'verilog-auto-star #[nil "\300 \205�\301 \207" [verilog-auto-star-safe verilog-auto-inst] 1 (#$ . 330025)])
#@12133 Expand AUTOINST statements, as part of \[verilog-auto].
Replace the pin connections to an instantiation or interface
declaration with ones automatically derived from the module or
interface header of the instantiated item.

If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
and delete them before saving unless `verilog-auto-star-save' is set.
See `verilog-auto-star' for more information.

The pins are printed in declaration order or alphabetically,
based on the `verilog-auto-inst-sort' variable.

To debug what file a submodule comes from, in a buffer with
AUTOINST, use \[verilog-goto-defun] to switch buffers to the
point containing the given symbol (i.e. a submodule name)'s
module definition.

Limitations:
  Module names must be resolvable to filenames by adding a
  `verilog-library-extensions', and being found in the same directory, or
  by changing the variable `verilog-library-flags' or
  `verilog-library-directories'.  Macros `modname are translated through the
  vh-{name} Emacs variable, if that is not found, it just ignores the \=`.

In templates you must have one signal per line, ending in a ), or ));,
  and have proper () nesting, including a final ); to end the template.

Typedefs must match `verilog-typedef-regexp', which is disabled by default.

SystemVerilog multidimensional input/output has only experimental support.

SystemVerilog .name syntax is used if `verilog-auto-inst-dot-name' is set.

Parameters referenced by the instantiation will remain symbolic, unless
  `verilog-auto-inst-param-value' is set.

Gate primitives (and/or) may have AUTOINST for the purpose of
  AUTOWIRE declarations, etc.  Gates are the only case when
  position based connections are passed.

The array part of arrayed instances are ignored; this may
  result in undesirable default AUTOINST connections; use a
  template instead.

For example, first take the submodule InstModule.v:

module InstModule (o,i);
           output [31:0] o;
           input i;
           wire [31:0] o = {32{i}};
        endmodule

This is then used in an upper level module:

module ExampInst (o,i);
           output o;
           input i;
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing \[verilog-auto] will make this into:

module ExampInst (o,i);
           output o;
           input i;
           InstModule instName
             (/*AUTOINST*/
              // Outputs
              .o        (o[31:0]),
              // Inputs
              .i        (i));
        endmodule

Where the list of inputs and outputs came from the inst module.

Exceptions:

Unless you are instantiating a module multiple times, or the module is
  something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
  It just makes for unmaintainable code.  To sanitize signal names, try
  vrename from URL `https://www.veripool.org'.

When you need to violate this suggestion there are two ways to list
  exceptions, placing them before the AUTOINST, or using templates.

Any ports defined before the /*AUTOINST*/ are not included in the list of
  automatics.  This is similar to making a template as described below, but
  is restricted to simple connections just like you normally make.  Also note
  that any signals before the AUTOINST will only be picked up by AUTOWIRE if
  you have the appropriate // Input or // Output comment, and exactly the
  same line formatting as AUTOINST itself uses.

InstModule instName
          (// Inputs
           .i           (my_i_dont_mess_with_it),
           /*AUTOINST*/
           // Outputs
           .o           (o[31:0]));

Templates:

For multiple instantiations based upon a single template, create a
  commented out template:

/* InstModule AUTO_TEMPLATE (
                .sig3   (sigz[]),
                );
        */

Templates go ABOVE the instantiation(s).  When an instantiation is
  expanded `verilog-mode' simply searches up for the closest template.
  Thus you can have multiple templates for the same module, just alternate
  between the template for an instantiation and the instantiation itself.
  (For backward compatibility if no template is found above, it
  will also look below, but do not use this behavior in new designs.)

The module name must be the same as the name of the module in the
  instantiation name, and the code "AUTO_TEMPLATE" must be in these exact
  words and capitalized.  Only signals that must be different for each
  instantiation need to be listed.

Inside a template, a [][] in a connection name will behave
  similarly to a [] for scalar or single-dimensional connection;
  for a multidimensional connection it will print a comment
  similar to that printed when a template is not used.  Generally
  it is a good idea to do this for all connections in a template,
  as then they will work for any width signal, and with AUTOWIRE.
  See PTL_BUS becoming PTL_BUSNEW below.

Inside a template, a [] in a connection name (with nothing else inside
  the brackets) will be replaced by the same bus subscript as it is being
  connected to, or the [] will be removed if it is a single bit signal.
  Generally it is a good idea to do this for all connections in a template,
  as then they will work for any width signal, and with AUTOWIRE.  See
  PTL_BUS becoming PTL_BUSNEW below.

If you have a complicated template, set `verilog-auto-inst-template-numbers'
  to see which regexps are matching.  Don't leave that mode set after
  debugging is completed though, it will result in lots of extra differences
  and merge conflicts.

Setting `verilog-auto-template-warn-unused' will report errors
  if any template lines are unused.

For example:

/* InstModule AUTO_TEMPLATE (
                .ptl_bus        (ptl_busnew[]),
                );
        */
        InstModule ms2m (/*AUTOINST*/);

Typing \[verilog-auto] will make this into:

InstModule ms2m (/*AUTOINST*/
            // Outputs
            .NotInTemplate      (NotInTemplate),
            .ptl_bus            (ptl_busnew[3:0]),
            ....

Multiple Module Templates:

The same template lines can be applied to multiple modules with
  the syntax as follows:

/* InstModuleA AUTO_TEMPLATE
           InstModuleB AUTO_TEMPLATE
           InstModuleC AUTO_TEMPLATE
           InstModuleD AUTO_TEMPLATE (
                .ptl_bus        (ptl_busnew[]),
                );
        */

Note there is only one AUTO_TEMPLATE opening parenthesis.

@ Templates:

It is common to instantiate a cell multiple times, so templates make it
  trivial to substitute part of the cell name into the connection name.

/* InstName AUTO_TEMPLATE <optional "REGEXP"> (
                .sig1   (sigx[@]),
                .sig2   (sigy[@"(% (+ 1 @) 4)"]),
                );
        */

If no regular expression is provided immediately after the AUTO_TEMPLATE
  keyword, then the @ character in any connection names will be replaced
  with the instantiation number; the first digits found in the cell's
  instantiation name.

If a regular expression is provided, the @ character will be replaced
  with the first () grouping that matches against the cell name.  Using a
  regexp of `$[0-9]+$' provides identical values for @ as when no
  regexp is provided.  If you use multiple layers of parenthesis,
  `test$[^0-9]+$_$[0-9]+$' would replace @ with non-number
  characters after test and before _, whereas
  `$test\([a-z]+$_$[0-9]+$\)' would replace @ with the entire
  match.

For example:

/* InstModule AUTO_TEMPLATE (
                .ptl_mapvalidx          (ptl_mapvalid[@]),
                .ptl_mapvalidp1x        (ptl_mapvalid[@"(% (+ 1 @) 4)"]),
                );
        */
        InstModule ms2m (/*AUTOINST*/);

Typing \[verilog-auto] will make this into:

InstModule ms2m (/*AUTOINST*/
            // Outputs
            .ptl_mapvalidx              (ptl_mapvalid[2]),
            .ptl_mapvalidp1x            (ptl_mapvalid[3]));

Note the @ character was replaced with the 2 from "ms2m".

Alternatively, using a regular expression for @:

/* InstModule AUTO_TEMPLATE "_$[a-z]+$" (
                .ptl_mapvalidx          (@_ptl_mapvalid),
                .ptl_mapvalidp1x        (ptl_mapvalid_@),
                );
        */
        InstModule ms2_FOO (/*AUTOINST*/);
        InstModule ms2_BAR (/*AUTOINST*/);

Typing \[verilog-auto] will make this into:

InstModule ms2_FOO (/*AUTOINST*/
            // Outputs
            .ptl_mapvalidx              (FOO_ptl_mapvalid),
            .ptl_mapvalidp1x            (ptl_mapvalid_FOO));
        InstModule ms2_BAR (/*AUTOINST*/
            // Outputs
            .ptl_mapvalidx              (BAR_ptl_mapvalid),
            .ptl_mapvalidp1x            (ptl_mapvalid_BAR));

Regexp Templates:

A template entry of the form

.pci_req$[0-9]+$_l      (pci_req_jtag_[\1]),

will apply an Emacs style regular expression search for any port beginning
  in pci_req followed by numbers and ending in _l and connecting that to
  the pci_req_jtag_[] net, with the bus subscript coming from what matches
  inside the first set of .  Thus pci_req2_l becomes pci_req_jtag_[2].

Since $[0-9]+$ is so common and ugly to read, a @ in the port name
  does the same thing.  (Note a @ in the connection/replacement text is
  completely different -- still use \1 there!)  Thus this is the same as
  the above template:

.pci_req@_l         (pci_req_jtag_[\1]),

Here's another example to remove the _l, useful when naming conventions
  specify _ alone to mean active low.  Note the use of [] to keep the bus
  subscript:

.$.*$_l         (\1_[]),

Lisp Templates:

First any regular expression template is expanded.

If the syntax @"( ... )" is found in a connection, the expression in
  quotes will be evaluated as a Lisp expression, with @ replaced by the
  instantiation number.  The MAPVALIDP1X example above would put @+1 modulo
  4 into the brackets.  Quote all double-quotes inside the expression with
  a leading backslash (\"...\"); or if the Lisp template is also a
  regexp template backslash the backslash quote (\\"...\\").

There are special variables defined that are useful in these
  Lisp functions:

vl-name        Name portion of the input/output port.
        vl-bits        Bus bits portion of the input/output port (`[2:0]').
        vl-mbits       Multidimensional array bits for port (`[2:0][3:0]').
        vl-width       Width of the input/output port (`3' for [2:0]).
                       May be a (...) expression if bits isn't a constant.
        vl-dir         Direction of the pin input/output/inout/interface.
        vl-modport     The modport, if an interface with a modport.
        vl-cell-type   Module name/type of the cell (`InstModule').
        vl-cell-name   Instance name of the cell (`instName').

Normal Lisp variables may be used in expressions.  See
  `verilog-read-defines' which can set vh-{definename} variables for use
  here.  Also, any comments of the form:

/*AUTO_LISP(setq foo 1)*/

will evaluate any Lisp expression inside the parenthesis between the
  beginning of the buffer and the point of the AUTOINST.  This allows
  functions to be defined or variables to be changed between instantiations.
  (See also `verilog-auto-insert-lisp' if you want the output from your
  lisp function to be inserted.)

Note that when using lisp expressions errors may occur when @ is not a
  number; you may need to use the standard Emacs Lisp functions
  `number-to-string' and `string-to-number'.

After the evaluation is completed, @ substitution and [] substitution
  occur.

For more information see the \[verilog-faq] and forums at URL
`https://www.veripool.org'.
(defalias 'verilog-auto-inst #[nil "\212`\212\306u\210\307\310!)\212\311 \210iT)\312\313\n\314\\\313\245_\\]\315 \211\316\f\317\")\320\21178\320\2119:\320\211;<\320\211=>\320?\321 7\322 :7@:A\323 \324H;\325e\"\210B\205h�\326 ?7C\235?\205\3277\330\"\2118\2058\316\f\317\")9\3317!\211D\324H\211E:\320FGHIJ\332HGF#,\203\265�\333\334:\"\202\266�\335=D\334H<*8\211\336H)\337\232\205\327�\3409\211K\336H);\"\341L\211M\203N\203>\204\360�\342 \210\330>\343\344!\210\345M\n
<=	?&\210*\3409\211K\313H);\"\337L\211M\2037>\204$\342 \210\330>\343\346!\210\345M\n
<=	?&\210*\3409\211K\324H);\"\347L\211M\203k>\204X\342 \210\330>\343\350!\210\345M\n
<=	?&\210*\3409\211K\334H);\"\351L\211M\203\237>\204\214\342 \210\330>\343\352!\210\345M\n
<=	?&\210*\3409\211K\353H);\"\354L\211M\203\323>\204\300\342 \210\330>\343\355!\210\345M\n
<=	?&\210*\212>\205\356\357\330#\210\360\334!\210\361c\210\362\363!\210\360\364!\210\362\365\320\330#\203\373\360\364!\210\362\366\320\330#\205\360\364!).\207" [pt for-star indent-pt verilog-auto-inst-column modi moddecls -2 looking-at "\\.\\*" verilog-backward-open-paren 16 8 7 verilog-modi-current verilog-modi-cache-results verilog-read-decls nil verilog-read-inst-module verilog-read-inst-name verilog-read-inst-pins 0 verilog-read-auto-lisp verilog-read-inst-param-value verilog-modi-lookup t verilog-read-auto-template string-match match-string 1 "" 3 "interface" verilog-signals-not-in "interfaced" verilog-auto-inst-first verilog-insert-indent "// Interfaced\n" verilog-auto-inst-port-list "// Interfaces\n" "output" "// Outputs\n" "inout" "// Inouts\n" 2 "input" "// Inputs\n" re-search-backward "," delete-char ");" search-forward "\n" -1 ")" ";" submod submodi submoddecls inst skip-pins tpl-list tpl-num did-first par-values vl-cell-type vl-cell-name verilog-auto-inst-param-value verilog-gate-keywords tpl-info tpl-regexp start string regexp verilog-case-fold case-fold-search decls vl-dir sig-list verilog-auto-inst-interfaced-ports] 9 (#$ . 330910)])
#@1242 Expand AUTOINSTPARAM statements, as part of \[verilog-auto].
Replace the parameter connections to an instantiation with ones
automatically derived from the module header of the instantiated netlist.

You may also provide an optional regular expression, in which
case only parameters matching the regular expression will be
included.

See \[verilog-auto-inst] for limitations, and templates to customize the
output.

For example, first take the submodule InstModule.v:

module InstModule (o,i);
           parameter PAR;
        endmodule

This is then used in an upper level module:

module ExampInstParam (o,i);
           parameter PAR;
           InstModule #(/*AUTOINSTPARAM*/)
                instName (/*AUTOINST*/);
        endmodule

Typing \[verilog-auto] will make this into:

module ExampInstParam (o,i);
           parameter PAR;
           InstModule #(/*AUTOINSTPARAM*/
                        // Parameters
                        .PAR    (PAR))
                instName (/*AUTOINST*/);
        endmodule

Where the list of parameter connections come from the inst module.

Templates:

You can customize the parameter connections using AUTO_TEMPLATEs,
  just as you would with \[verilog-auto-inst].
(defalias 'verilog-auto-inst-param #[nil "\212\306\307\310\"\211@`\212\311 \210iT)\f\312\313\314\\\313\245_\\]\315 \211\316
\317\")-\320\211./\320\21101\320\21123\320\21145\212\321\320\21167\320\n\204s�\322	76#\203s�\323\307\224!\203l�\322\324\320\325#\210\202N�\307\225\211\203R�\n,\210\326 ).\212\321\320\21167\320\n\204\253�\322	76#\203\253�\323\307\224!\203\244�\322\324\320\325#\210\202\206�\307\225\211\203\212�\n,\210\327 )1.819\330 \307H2\331e\n\"\210\332.\325\"\211/\205w/\316
\317\")0\333.!\211:\307H\211;1\320<=>?\334	=<#,\203\335\3101\"\202\3364:\310H3*\3370\211@\314H)2\"\340AB	\203,\341B	\"BB\203O5\204<\342 \210\3255\343\344!\210\345B-34\320\211&\210*\2125\205v\346\347\n\325#\210\350\310!\210\351c\210\352\353!\210\350\354!\210\352\351\320\325#\205v\350\354!).\207" [params regexp pt indent-pt verilog-auto-inst-column modi verilog-read-auto-params 0 1 verilog-backward-open-paren 16 8 7 verilog-modi-current verilog-modi-cache-results verilog-read-decls nil "[(;]" re-search-forward verilog-inside-comment-or-string-p "[/\"\n]" t verilog-read-inst-module verilog-read-inst-name verilog-read-inst-pins verilog-read-auto-lisp verilog-modi-lookup verilog-read-auto-template string-match match-string "" verilog-signals-not-in "parameter" verilog-signals-matching-regexp verilog-auto-inst-first verilog-insert-indent "// Parameters\n" verilog-auto-inst-port-list re-search-backward "," delete-char ")" search-forward "\n" -1 moddecls submod submodi submoddecls inst skip-pins tpl-list tpl-num did-first noerror bound vl-cell-type vl-cell-name tpl-info tpl-regexp start string verilog-case-fold case-fold-search decls vl-dir sig-list] 9 (#$ . 345171)])
#@826 Expand AUTOREG statements, as part of \[verilog-auto].
Make reg statements for any output that isn't already declared,
and isn't a wire output from a block.  `verilog-auto-wire-type'
may be used to change the datatype of the declarations.

Limitations:
  This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').

This does NOT work on memories, declare those yourself.

An example:

module ExampReg (o,i);
           output o;
           input i;
           /*AUTOREG*/
           always o = i;
        endmodule

Typing \[verilog-auto] will make this into:

module ExampReg (o,i);
           output o;
           input i;
           /*AUTOREG*/
           // Beginning of automatic regs
           reg          o;
           // End of automatics
           always o = i;
        endmodule
(defalias 'verilog-auto-reg #[nil "\212\306 \307 \211\310	\311\")	\310	\312\")\313\n\211\314H)\315\316\317\n\211\314H)\"\n\211\320H)\n\211\321H)\n\211\322H)\n\211\323H)\211\324H)\211\314H)\211\325H)&\"\211\205n�\326 \210\327\330!\210\331	\332\333%\210\327\334!.\207" [indent-pt modi moddecls modsubdecls decls subdecls current-indentation verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-read-sub-decls verilog-signals-not-in 0 append verilog-signals-with verilog-sig-type 3 5 6 7 4 1 verilog-forward-or-insert-line verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n" verilog-insert-definition "reg" nil "// End of automatics\n" sig-list] 13 (#$ . 348170)])
#@1185 Expand AUTOREGINPUT statements, as part of \[verilog-auto].
Make reg statements instantiation inputs that aren't already
declared or assigned to.  This is useful for making a top level
shell for testing the module that is to be instantiated.

Limitations:
  This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').

This does NOT work on memories, declare those yourself.

Assignments cause the assigned-to variable not to be declared unless
  the name matches `verilog-auto-reg-input-assigned-ignore-regexp'.

An example (see `verilog-auto-inst' for what else is going on here):

module InstModule (input i);
        endmodule

module ExampRegInput ();
           /*AUTOREGINPUT*/
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing \[verilog-auto] will make this into:

module ExampRegInput ();
           /*AUTOREGINPUT*/
           // Beginning of automatic reg inputs
           reg          i;      // To instName of InstModule.v
           // End of automatics
           InstModule instName
             (/*AUTOINST*/
              // Inputs
              .i                (i));
        endmodule
(defalias 'verilog-auto-reg-input #[nil "\212\306 \307 \211\310	\311\")	\310	\312\")\313\314\315\211\316H)\211\317H)\"\315\320\n!\321\n\211\322H)\"\"\"!\211\205Q�\323 \210\324\325!\210\326	\327\330%\210\324\331!.\207" [indent-pt modi moddecls modsubdecls subdecls decls current-indentation verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-read-sub-decls verilog-signals-combine-bus verilog-signals-not-in append 2 1 verilog-decls-get-signals verilog-signals-not-matching-regexp 5 verilog-forward-or-insert-line verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n" verilog-insert-definition "reg" nil "// End of automatics\n" verilog-auto-reg-input-assigned-ignore-regexp sig-list] 9 (#$ . 349756)])
#@37 Prepare variables due to AUTOLOGIC.
(defalias 'verilog-auto-logic-setup #[nil "?\205\f�\301\300!\210\302\211\207" [verilog-auto-wire-type make-local-variable "logic"] 2 (#$ . 351744)])
#@372 Expand AUTOLOGIC statements, as part of \[verilog-auto].
Make wire statements using the SystemVerilog logic keyword.
This is currently equivalent to:

/*AUTOWIRE*/

with the below at the bottom of the file

// Local Variables:
    // verilog-auto-wire-type:"logic"
    // End:

In the future AUTOLOGIC may declare additional identifiers,
while AUTOWIRE will not.
(defalias 'verilog-auto-logic #[nil "\212\300 \210\301 )\207" [verilog-auto-logic-setup verilog-auto-wire] 1 (#$ . 351938)])
#@1459 Expand AUTOWIRE statements, as part of \[verilog-auto].
Make wire statements for instantiations outputs that aren't
already declared.  `verilog-auto-wire-type' may be used to change
the datatype of the declarations.

Limitations:
  This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
  and all buses must have widths, such as those from AUTOINST, or using []
  in AUTO_TEMPLATEs.

This does NOT work on memories or SystemVerilog .name connections,
  declare those yourself.

Verilog mode will add "Couldn't Merge" comments to signals it cannot
  determine how to bus together.  This occurs when you have ports with
  non-numeric or non-sequential bus subscripts.  If Verilog mode
  mis-guessed, you'll have to declare them yourself.

An example (see `verilog-auto-inst' for what else is going on here):

module ExampWire (i);
           input i;
           /*AUTOWIRE*/
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing \[verilog-auto] will make this into:

module ExampWire (i);
           input i;
           /*AUTOWIRE*/
           // Beginning of automatic wires
           wire [31:0]  o;      // From instName of InstModule.v
           // End of automatics
           InstModule instName
             (/*AUTOINST*/
              // Outputs
              .o        (o[31:0]),
              // Inputs
              .i        (i));
           wire o = | ov;
        endmodule
(defalias 'verilog-auto-wire #[nil "\212\306 \307 \211\310	\311\")	\310	\312\")\313\314\315\211\316H)\211\317H)\"\320\n!\"!\211\205C�\321 \210\322\323!\210\324	
\325\326%\210\322\327!.\207" [indent-pt modi moddecls modsubdecls subdecls sig-list current-indentation verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-read-sub-decls verilog-signals-combine-bus verilog-signals-not-in append 0 1 verilog-decls-get-signals verilog-forward-or-insert-line verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n" verilog-insert-definition "wire" nil "// End of automatics\n"] 7 (#$ . 352442)])
#@1755 Expand AUTOOUTPUT statements, as part of \[verilog-auto].
Make output statements for any output signal from an /*AUTOINST*/ that
isn't an input to another AUTOINST.  This is useful for modules which
only instantiate other modules.

Limitations:
  This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').

If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
  instantiation, all bets are off.  (For example due to an AUTO_TEMPLATE).

Typedefs must match `verilog-typedef-regexp', which is disabled by default.

Types are added to declarations if an AUTOLOGIC or
  `verilog-auto-wire-type' is set to logic.

Signals matching `verilog-auto-output-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

module InstModule (output o);
        endmodule

module ExampOutput
           (/*AUTOOUTPUT*/
           );
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing \[verilog-auto] will make this into:

module ExampOutput
          (/*AUTOOUTPUT*/
           // Beginning of automatic outputs
           output          o    // From instName of InstModule.v
           // End of automatics
           );
          InstModule instName
            (/*AUTOINST*/
             // Outputs
             .o          (o));
        endmodule

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included.  For example the
same expansion will result from only extracting outputs starting with ov:

/*AUTOOUTPUT("^ov")*/
(defalias 'verilog-auto-output #[nil "\212\306 \307\310\311\"\211@\312 \313 \211\314\f\315\")\f\314\f\316\")\317\211\310H)\320
\211\310H)
\211\311H)
\211\321H)\211\321H)\211\311H)%\"\n\203a�\322\n\"\323 \"\324 \210\203s�\325 \210\203\211�\326\327!\210\330\f\331%\210\326\332!\210\205\217�\333 .	\207" [indent-pt params regexp v2k modi moddecls current-indentation verilog-read-auto-params 0 1 verilog-in-paren-quick verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-read-sub-decls verilog-signals-not-in append 2 verilog-signals-matching-regexp verilog-signals-not-matching-regexp verilog-forward-or-insert-line verilog-repair-open-comma verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n" verilog-insert-definition "output" "// End of automatics\n" verilog-repair-close-comma modsubdecls subdecls decls sig-list verilog-auto-output-ignore-regexp] 10 (#$ . 354579)])
#@1253 Expand AUTOOUTPUTEVERY statements, as part of \[verilog-auto].
Make output statements for any signals that aren't primary inputs or
outputs already.  This makes every signal in the design an output.  This is
useful to get synthesis to preserve every signal in the design, since it
won't optimize away the outputs.

An example:

module ExampOutputEvery (o,i,tempa,tempb);
           output o;
           input i;
           /*AUTOOUTPUTEVERY*/
           wire tempa = i;
           wire tempb = tempa;
           wire o = tempb;
        endmodule

Typing \[verilog-auto] will make this into:

module ExampOutputEvery (
           /*AUTOOUTPUTEVERY*/
           // Beginning of automatic outputs (every signal)
           output          o,
           output          tempa,
           output          tempb,
           // End of automatics
           input i
           );
           wire tempa = i;
           wire tempb = tempa;
           wire o = tempb;
        endmodule

/*AUTOOUTPUTEVERY("^ov")*/
(defalias 'verilog-auto-output-every #[nil "\212\306 \307\310\311\"\211@\312 \313 \211\314\f\315\")\316\317\320
!\321
!\"!\n\2031�\322\n\"\323\"\324 \210\203C�\325 \210\203Y�\326\327!\210\330\f\331%\210\326\332!\210\205_�\333 .\207" [indent-pt params regexp v2k modi moddecls current-indentation verilog-read-auto-params 0 1 verilog-in-paren-quick verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-signals-combine-bus verilog-signals-not-in verilog-decls-get-signals verilog-decls-get-ports verilog-signals-matching-regexp verilog-signals-not-matching-regexp verilog-forward-or-insert-line verilog-repair-open-comma verilog-insert-indent "// Beginning of automatic outputs (every signal)\n" verilog-insert-definition "output" "// End of automatics\n" verilog-repair-close-comma sig-list verilog-auto-output-ignore-regexp] 7 (#$ . 357319)])
#@1783 Expand AUTOINPUT statements, as part of \[verilog-auto].
Make input statements for any input signal into an /*AUTOINST*/ that
isn't declared elsewhere inside the module.  This is useful for modules which
only instantiate other modules.

Limitations:
  This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').

If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
  instantiation, all bets are off.  (For example due to an AUTO_TEMPLATE).

Typedefs must match `verilog-typedef-regexp', which is disabled by default.

Types are added to declarations if an AUTOLOGIC or
  `verilog-auto-wire-type' is set to logic.

Signals matching `verilog-auto-input-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

module InstModule (input i);
        endmodule

module ExampInput (
           /*AUTOINPUT*/
           );
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing \[verilog-auto] will make this into:

module ExampInput (
           /*AUTOINPUT*/
           // Beginning of automatic inputs (from unused autoinst inputs)
           input           i       // To instName of InstModule.v
           // End of automatics
           );
           InstModule instName
             (/*AUTOINST*/
              // Inputs
              .i        (i));
        endmodule

/*AUTOINPUT("^i")*/
(defalias 'verilog-auto-input #[nil "\212\306 \307\310\311\"\211@\312 \313 \211\314\f\315\")\f\314\f\316\") \317 \211!\320H)\321
\211\"\320H)
\211\"\311H)
\211\"\310H)
\211\"\322H)
\211\"\323H)
\211\"\324H) \211!\325H) \211!\310H) \211!\311H)&	\"#\n\203�\326#\n\"#\327#$\"#\330 \210\203\221�\331 \210#\203\247�\332\333!\210\334\f#\335%\210\332\336!\210\205\255�\337 .	\207" [indent-pt params regexp v2k modi moddecls current-indentation verilog-read-auto-params 0 1 verilog-in-paren-quick verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-read-sub-decls verilog-signals-not-in 2 append 3 6 7 4 verilog-signals-matching-regexp verilog-signals-not-matching-regexp verilog-forward-or-insert-line verilog-repair-open-comma verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n" verilog-insert-definition "input" "// End of automatics\n" verilog-repair-close-comma modsubdecls subdecls decls sig-list verilog-auto-input-ignore-regexp] 14 (#$ . 359472)])
#@1699 Expand AUTOINOUT statements, as part of \[verilog-auto].
Make inout statements for any inout signal in an /*AUTOINST*/ that
isn't declared elsewhere inside the module.

Limitations:
  This ONLY detects inouts of AUTOINSTants (see `verilog-read-sub-decls').

If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
  instantiation, all bets are off.  (For example due to an AUTO_TEMPLATE).

Typedefs must match `verilog-typedef-regexp', which is disabled by default.

Types are added to declarations if an AUTOLOGIC or
  `verilog-auto-wire-type' is set to logic.

Signals matching `verilog-auto-inout-ignore-regexp' are not included.

An example (see `verilog-auto-inst' for what else is going on here):

module InstModule (inout io);
        endmodule

module ExampInout (
           /*AUTOINOUT*/
           );
           InstModule instName
             (/*AUTOINST*/);
        endmodule

Typing \[verilog-auto] will make this into:

module ExampInout (
           /*AUTOINOUT*/
           // Beginning of automatic inouts
           inout           io      // To/From instName of InstModule.v
           // End of automatics
           );
           InstModule instName
             (/*AUTOINST*/
              // Inouts
              .io       (io));
        endmodule

/*AUTOINOUT("^i")*/
(defalias 'verilog-auto-inout #[nil "\212\306 \307\310\311\"\211@\312 \313 \211\314\f\315\")\f\314\f\316\")\317\211\311H)\320
\211\310H)
\211\311H)
\211\321H)\211\321H)\211\310H)%\"\n\203a�\322\n\"\323 \"\324 \210\203s�\325 \210\203\211�\326\327!\210\330\f\331%\210\326\332!\210\205\217�\333 .	\207" [indent-pt params regexp v2k modi moddecls current-indentation verilog-read-auto-params 0 1 verilog-in-paren-quick verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-read-sub-decls verilog-signals-not-in append 2 verilog-signals-matching-regexp verilog-signals-not-matching-regexp verilog-forward-or-insert-line verilog-repair-open-comma verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n" verilog-insert-definition "inout" "// End of automatics\n" verilog-repair-close-comma modsubdecls subdecls decls sig-list verilog-auto-inout-ignore-regexp] 10 (#$ . 362306)])
#@2683 Expand AUTOINOUTMODULE statements, as part of \[verilog-auto].
Take input/output/inout statements from the specified module and insert
into the current module.  This is useful for making null templates and
shell modules which need to have identical I/O with another module.
Any I/O which are already defined in this module will not be redefined.
For the complement of this function, see `verilog-auto-inout-comp',
and to make monitors with all inputs, see `verilog-auto-inout-in'.

Limitations:
  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial buses is not supported.

Module names must be resolvable to filenames.  See `verilog-auto-inst'.

Signals are not inserted in the same order as in the original module,
  though they will appear to be in the same order to an AUTOINST
  instantiating either module.

Signals declared as "output reg" or "output wire" etc will
  lose the wire/reg declaration so that shell modules may
  generate those outputs differently.  However, "output logic"
  is propagated.

An example:

module ExampMain
          (input i,
           output o,
           inout io);
        endmodule

module ExampShell (/*AUTOARG*/);
           /*AUTOINOUTMODULE("ExampMain")*/
        endmodule

Typing \[verilog-auto] will make this into:

module ExampShell (/*AUTOARG*/o, io, o);
           /*AUTOINOUTMODULE("ExampMain")*/
           // Beginning of automatic in/out/inouts
           output o;
           inout io;
           input i;
           // End of automatics
        endmodule

/*AUTOINOUTMODULE("ExampMain","^i")*/

You may also provide an optional third argument regular
expression, in which case only signals which have that pin
direction and data type matching that regular expression will be
included.  This matches against everything before the signal name
in the declaration, for example against "input" (single
bit), "output logic" (direction and type) or
"output [1:0]" (direction and implicit type).  You also
probably want to skip spaces in your regexp.

For example, the below will result in matching the output "o"
against the previous example's module:

/*AUTOINOUTMODULE("ExampMain","","^output.*")*/

You may also provide an optional fourth argument regular
expression, which if not "" only signals which do NOT match
that expression are included.
(defalias 'verilog-auto-inout-module #[(&optional complement all-in) "\212\306\307\310\"\211@A@\3118\3128\313\314	\315\"\211\205\224\316 %\317 &\320 \211''\321'\322\")(
'\321'\322\"))\323*\203e�\324)\211+\311H))\211+\307H))\211+\325H)#\202}�,\203u�)\211+\325H)\202}�)\211+\311H)\324(\211+\311H)!\"-\323*\203\224�\313\202\254�,\203\244�)\211+\311H)\202\254�)\211+\325H)\324(\211+\325H)!\".\323*\203\303�\313\202\313�)\211+\307H)\324(\211+\307H)!\"/\323)\211+\326H)\324(\211+\326H)!\"0\307y\210\327\330\331\332-\n\"\333#\f\"!-\327\330\331\332.\n\"\334#\f\"!.\327\330\331\332/\n\"\335#\f\"!/\330\331\3320\n\"\336#\f\"0&\2037\337 \210-\204K.\204K/\204K0\203\213\340\341!\210\342'.\334%&\315&\210\342'/\335%&\315&\210\342'-\333%&\315&\210\342'0\336%&\315&\210\340\343!\210&\205\222\344 .	.\207" [params submod regexp direction-re not-re submodi verilog-read-auto-params 1 4 2 3 nil verilog-modi-lookup t current-indentation verilog-in-paren-quick verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-signals-not-in append 0 8 verilog-signals-edit-wire-reg verilog-signals-not-matching-regexp verilog-signals-matching-dir-re verilog-signals-matching-regexp "input" "output" "inout" "interface" verilog-repair-open-comma verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n" verilog-insert-definition "// End of automatics\n" verilog-repair-close-comma indent-pt v2k modi moddecls submoddecls all-in decls complement sig-list-i sig-list-o sig-list-io sig-list-if] 8 (#$ . 364985)])
#@2457 Expand AUTOINOUTCOMP statements, as part of \[verilog-auto].
Take input/output/inout statements from the specified module and
insert the inverse into the current module (inputs become outputs
and vice-versa.)  This is useful for making test and stimulus
modules which need to have complementing I/O with another module.
Any I/O which are already defined in this module will not be
redefined.  For the complement of this function, see
`verilog-auto-inout-module'.

Limitations:
  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial buses is not supported.

Module names must be resolvable to filenames.  See `verilog-auto-inst'.

Signals are not inserted in the same order as in the original module,
  though they will appear to be in the same order to an AUTOINST
  instantiating either module.

An example:

module ExampMain
          (input i,
           output o,
           inout io);
        endmodule

module ExampBench (/*AUTOARG*/);
           /*AUTOINOUTCOMP("ExampMain")*/
        endmodule

Typing \[verilog-auto] will make this into:

module ExampShell (/*AUTOARG*/i, io, o);
           /*AUTOINOUTCOMP("ExampMain")*/
           // Beginning of automatic in/out/inouts
           output i;
           inout io;
           input o;
           // End of automatics
        endmodule

/*AUTOINOUTCOMP("ExampMain","^i")*/

You may also provide an optional third argument regular
expression, in which case only signals which have that pin
direction and data type matching that regular expression will be
included.  This matches against everything before the signal name
in the declaration, for example against "input" (single
bit), "output logic" (direction and type)
or "output [1:0]" (direction and implicit type).  You also
probably want to skip spaces in your regexp.

For example, the below will result in matching the output "o"
against the previous example's module:

/*AUTOINOUTCOMP("ExampMain","","^output.*")*/

You may also provide an optional fourth argument regular
expression, which if not "" only signals which do NOT match
that expression are included.
(defalias 'verilog-auto-inout-comp #[nil "\300\301\302\"\207" [verilog-auto-inout-module t nil] 3 (#$ . 369307)])
#@1629 Expand AUTOINOUTIN statements, as part of \[verilog-auto].
Take input/output/inout statements from the specified module and
insert them as all inputs into the current module.  This is
useful for making monitor modules which need to see all signals
as inputs based on another module.  Any I/O which are already
defined in this module will not be redefined.  See also
`verilog-auto-inout-module'.

Limitations:
  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

Concatenation and outputting partial buses is not supported.

Module names must be resolvable to filenames.  See `verilog-auto-inst'.

Signals are not inserted in the same order as in the original module,
  though they will appear to be in the same order to an AUTOINST
  instantiating either module.

An example:

module ExampMain
          (input i,
           output o,
           inout io);
        endmodule

module ExampInoutIn (/*AUTOARG*/);
           /*AUTOINOUTIN("ExampMain")*/
        endmodule

Typing \[verilog-auto] will make this into:

module ExampInoutIn (/*AUTOARG*/i, io, o);
           /*AUTOINOUTIN("ExampMain")*/
           // Beginning of automatic in/out/inouts
           input i;
           input io;
           input o;
           // End of automatics
        endmodule

/*AUTOINOUTIN("ExampMain","^i")*/
(defalias 'verilog-auto-inout-in #[nil "\300\301\302\"\207" [verilog-auto-inout-module nil t] 3 (#$ . 371885)])
#@1580 Expand AUTOINOUTPARAM statements, as part of \[verilog-auto].
Take input/output/inout statements from the specified module and insert
into the current module.  This is useful for making null templates and
shell modules which need to have identical I/O with another module.
Any I/O which are already defined in this module will not be redefined.
For the complement of this function, see `verilog-auto-inout-comp',
and to make monitors with all inputs, see `verilog-auto-inout-in'.

Limitations:
  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

Module names must be resolvable to filenames.  See `verilog-auto-inst'.

Parameters are inserted in the same order as in the original module.

Parameters do not have values, which is SystemVerilog 2009 syntax.

An example:

module ExampMain ();
          parameter PARAM = 22;
        endmodule

module ExampInoutParam ();
           /*AUTOINOUTPARAM("ExampMain")*/
        endmodule

Typing \[verilog-auto] will make this into:

module ExampInoutParam ();
           /*AUTOINOUTPARAM("ExampMain")*/
           // Beginning of automatic parameters (from specific module)
           parameter       PARAM;
           // End of automatics
        endmodule

You may also provide an optional regular expression, in which case only
parameters matching the regular expression will be included.  For example the
same expansion will result from only extracting parameters starting with i:

/*AUTOINOUTPARAM("ExampMain","^i")*/
(defalias 'verilog-auto-inout-param #[nil "\212\306\307\310\"\211@A@\311\312	\313\"\211\205\200�\314 \315 \316 \211\317\320\")\317\320\")\321\211\322H)\323\211\322H)!\" \307y\210\324 \n\" 
\203_�\325 \210 \203x�\326\327!\210\330 \331\f
\313&\210\326\332!\210
\205~�\333 .-\207" [params submod regexp submodi indent-pt v2k verilog-read-auto-params 1 2 nil verilog-modi-lookup t current-indentation verilog-in-paren-quick verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-signals-not-in 7 append verilog-signals-matching-regexp verilog-repair-open-comma verilog-insert-indent "// Beginning of automatic parameters (from specific module)\n" verilog-insert-definition "parameter" "// End of automatics\n" verilog-repair-close-comma modi moddecls submoddecls decls sig-list-p] 8 (#$ . 373633)])
#@1831 Expand AUTOINOUTMODPORT statements, as part of \[verilog-auto].
Take input/output/inout statements from the specified interface
and modport and insert into the current module.  This is useful
for making verification modules that connect to UVM interfaces.

The first parameter is the name of an interface.

The second parameter is a regexp of modports to read from in
  that interface.

The optional third parameter is a regular expression, and only
  signals matching the regular expression will be included.

Limitations:
  If placed inside the parenthesis of a module declaration, it creates
  Verilog 2001 style, else uses Verilog 1995 style.

Interface names must be resolvable to filenames.  See `verilog-auto-inst'.

As with other autos, any inputs/outputs declared in the module
will suppress the AUTO from redeclaring an inputs/outputs by
the same name.

An example:

interface ExampIf
          ( input logic clk );
           logic        req_val;
           logic [7:0]  req_dat;
           clocking mon_clkblk @(posedge clk);
              input     req_val;
              input     req_dat;
           endclocking
           modport mp(clocking mon_clkblk);
        endinterface

module ExampMain
        ( input clk,
          /*AUTOINOUTMODPORT("ExampIf", "mp")*/
        );
        endmodule

Typing \[verilog-auto] will make this into:

module ExampMain
        ( input clk,
          /*AUTOINOUTMODPORT("ExampIf", "mp")*/
          // Beginning of automatic in/out/inouts (from modport)
          input        req_val,
          input [7:0]  req_dat
          // End of automatics
        );
        endmodule

If the modport is part of a UVM monitor/driver class, this
creates a wrapper module that may be used to instantiate the
driver/monitor using AUTOINST in the testbench.
(defalias 'verilog-auto-inout-modport #[nil "\212\306\307\310\"\211@A@\3078\311\211\312	\313\"\211\205\"\314 $\315 %\316 \211&&\317&\320\")'
&\317&\320\")(\321
\n\")\322(\211*\310H)\323)\211*\307H)\324\325(!\325'!\"\"\"+\322(\211*\310H)\323)\211*\326H)\324\325(!\325'!\"\"\",\322(\211*\310H)\323)\211*\327H)\324\325(!\325'!\"\"\"-\327y\210\330\331\332+\"\333\f#!+\330\331\332,\"\334\f#!,\330\331\332-\"\335\f#!-%\203\330�\336 \210+\204\347�,\204\347�-\203\337\340!\210\341&,\334$%\313&\210\341&-\335$%\313&\210\341&+\333$%\313&\210\337\342!\210%\205 \343 .	.\207" [params submod modport-re regexp direction-re submodi verilog-read-auto-params 2 3 nil verilog-modi-lookup t current-indentation verilog-in-paren-quick verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-modi-modport-lookup verilog-signals-in verilog-signals-not-in append verilog-decls-get-ports 0 1 verilog-signals-edit-wire-reg verilog-signals-matching-dir-re verilog-signals-matching-regexp "input" "output" "inout" verilog-repair-open-comma verilog-insert-indent "// Beginning of automatic in/out/inouts (from modport)\n" verilog-insert-definition "// End of automatics\n" verilog-repair-close-comma indent-pt v2k modi moddecls submoddecls submodportdecls decls sig-list-i sig-list-o sig-list-io] 9 (#$ . 376075)])
#@1511 Expand AUTOINSERTLISP statements, as part of \[verilog-auto].
The Lisp code provided is called before other AUTOS are expanded,
and the Lisp code generally will call `insert' to insert text
into the current file beginning on the line after the
AUTOINSERTLISP.

See also AUTOINSERTLAST and `verilog-auto-insert-last' which
executes after (as opposed to before) other AUTOs.

See also AUTO_LISP, which takes a Lisp expression and evaluates
it during `verilog-auto-inst' but does not insert any text.

An example:

module ExampInsertLisp;
           /*AUTOINSERTLISP(my-verilog-insert-hello "world")*/
        endmodule

// For this example we declare the function in the
        // module's file itself.  Often you'd define it instead
        // in a site-start.el or init file.
        /*
         Local Variables:
         eval:
           (defun my-verilog-insert-hello (who)
             (insert (concat "initial $write(\"hello " who "\");\n")))
         End:
        */

Typing \[verilog-auto] will call my-verilog-insert-hello and
expand the above into:

/*AUTOINSERTLISP(my-verilog-insert-hello "world")*/
           // Beginning of automatic insert lisp
           initial $write("hello world");
           // End of automatics

You can also call an external program and insert the returned
text:

/*AUTOINSERTLISP(insert (shell-command-to-string "echo //hello"))*/
           // Beginning of automatic insert lisp
           //hello
           // End of automatics
(defalias 'verilog-auto-insert-lisp #[nil "\212\305 \212\306\307!\210\310u\210`)\212	b\210\311\312!\210`)\313\n	\"\314 \210\315\316!\210\315\317!\210\320y\210\321\322!!\210\320y\210\310\323 -\207" [indent-pt cmd-end-pt cmd-beg-pt cmd verilog-scan-cache-tick current-indentation search-backward ")" nil backward-sexp 1 buffer-substring-no-properties verilog-forward-or-insert-line verilog-insert-indent "// Beginning of automatic insert lisp\n" "// End of automatics\n" -1 eval read verilog-delete-empty-auto-pair] 3 (#$ . 379294)])
#@515 Expand AUTOINSERTLAST statements, as part of \[verilog-auto].
The Lisp code provided is called after all other AUTOS have been
expanded, and the Lisp code generally will call `insert' to
insert text into the current file beginning on the line after the
AUTOINSERTLAST.

Other than when called (after AUTOs are expanded), the functionality
is otherwise identical to AUTOINSERTLISP and `verilog-auto-insert-lisp' which
executes before (as opposed to after) other AUTOs.

See `verilog-auto-insert-lisp' for examples.
(defalias 'verilog-auto-insert-last #[nil "\300 \207" [verilog-auto-insert-lisp] 1 (#$ . 381349)])
#@53 Return list of signals for current AUTOSENSE block.
(defalias 'verilog-auto-sense-sigs #[(moddecls presense-sigs) "\212\306\307!\210\310 )\311\312\211\313H)\314\n?\205�\211\315H)\n?\205(�\211\316H)\211\317H)\211\320H)\211\321H)
&\"!)\207" [sigss sigs verilog-auto-sense-include-inputs moddecls decls presense-sigs search-forward ")" verilog-read-always-signals verilog-signals-not-params verilog-signals-not-in 3 append 0 1 2 6 7] 11 (#$ . 381968)])
#@2161 Expand AUTOSENSE statements, as part of \[verilog-auto].
Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
with one automatically derived from all inputs declared in the always
statement.  Signals that are generated within the same always block are NOT
placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
Long lines are split based on the `fill-column', see \[set-fill-column].

Limitations:
  Verilog does not allow memories (multidimensional arrays) in sensitivity
  lists.  AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.

Constant signals:
  AUTOSENSE cannot always determine if a \=`define is a constant or a signal
  (it could be in an include file for example).  If a \=`define or other signal
  is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
  declaration anywhere in the module (parenthesis are required):

/* AUTO_CONSTANT ( \=`this_is_really_constant_dont_autosense_it ) */

Better yet, use a parameter, which will be understood to be constant
  automatically.

OOps!
  If AUTOSENSE makes a mistake, please report it.  (First try putting
  a begin/end after your always!) As a workaround, if a signal that
  shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
  If a signal should be in the sensitivity list wasn't, placing it before
  the /*AUTOSENSE*/ comment will prevent it from being deleted when the
  autos are updated (or added if it occurs there already).

An example:

always @ (/*AS*/) begin
              /*AUTO_CONSTANT (\=`constant) */
              outin = ina | inb | \=`constant;
              out = outin;
           end

Typing \[verilog-auto] will make this into:

always @ (/*AS*/ina or inb) begin
              /*AUTO_CONSTANT (\=`constant) */
              outin = ina | inb | \=`constant;
              out = outin;
           end

Note in Verilog 2001, you can often get the same result from the new @*
operator.  (This was added to the language in part due to AUTOSENSE!)

always @* begin
              outin = ina | inb | \=`constant;
              out = outin;
           end
(defalias 'verilog-auto-sense #[nil "\212\212\306\307\310\307\204-�\311\n	#\203-�\312\313\224!\203&�\311\314\307\310#\210\202\n�\313\224\211\203�,\210`)\212\fb\203>�iT\206@�\315 )\316 \211%%\317%\320\")&\321&\211'\322H)!(\307\211)*\307+\323\212\324\f`\")!+\325&+\")(\203\230�)G,\326)(\"),)G=\204\227�\327\330!\210)+\203l\212`b\210\331\f\310\307\204\314�\311\n	#\203\314�\312\313\224!\203\305�\311\314\307\310#\210\202\251�\313\224\211\203\255�,\210\332\f\310\307\204\372�\311\n	#\203\372�\312\313\224!\203\363�\311\314\307\310#\210\202\327�\313\224\211\203\333�,\210\333\334!\203b\331\f\310\307\204.\311\n	#\203.\312\313\224!\203'\311\314\307\310#\210\202\313\224\211\203,\210\332\f\310\307\204\\\311\n	#\203\\\312\313\224!\203U\311\314\307\310#\210\2029\313\224\211\203=,\210\202\375�\333\335!)\204l\310*\336)\337\"))\205\271\340\341i)@\211-@)G#.V\203\234\342c\210
j\210*\203\244\343c\210\202\244*\203\244\344c\210)@\211-@)c\210)A)\310*\202s.	\207" [noerror bound regexp pt start-pt indent-pt "(" nil t re-search-backward verilog-inside-comment-or-string-p 0 "[/\"]" current-indentation verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-signals-memory 3 verilog-signals-from-signame verilog-read-signals verilog-auto-sense-sigs verilog-signals-not-in verilog-insert " /*memory or*/ " "[a-zA-Z0-9$_.%`]+" "\\s-" looking-at "\\s-`endif" "\\s-or\\b" sort verilog-signals-sort-compare + 4 "\n" "or " " or " modi moddecls decls sig-memories sig-list not-first presense-sigs tlen sig fill-column] 5 (#$ . 382441)])
#@2158 Expand AUTORESET statements, as part of \[verilog-auto].
Replace the /*AUTORESET*/ comment with code to initialize all
registers set elsewhere in the always block.

Limitations:
  AUTORESET will not clear memories.

AUTORESET uses <= if the signal has a <= assignment in the block,
  else it uses =.

If <= is used, all = assigned variables are ignored if
  `verilog-auto-reset-blocking-in-non' is nil; they are presumed
  to be temporaries.

/*AUTORESET*/ presumes that any signals mentioned between the previous
begin/case/if statement and the AUTORESET comment are being reset manually
and should not be automatically reset.  This includes omitting any signals
used on the right hand side of assignments.

By default, AUTORESET will include the width of the signal in the
autos, SystemVerilog designs may want to change this.  To control
this behavior, see `verilog-auto-reset-widths'.  In some cases
AUTORESET must use a \='0 assignment and it will print NOWIDTH; use
`verilog-auto-reset-widths' unbased to prevent this.

AUTORESET ties signals to deasserted, which is presumed to be zero.
Signals that match `verilog-active-low-regexp' will be deasserted by tying
them to a one.

AUTORESET may try to reset arrays or structures that cannot be
reset by a simple assignment, resulting in compile errors.  This
is a feature to be taken as a hint that you need to reset these
signals manually (or put them into a "\=`ifdef NEVER signal<=\=`0;
\=`endif" so Verilog-Mode ignores them.)

An example:

module ExampReset ();
           always @(posedge clk or negedge reset_l) begin
              if (!reset_l) begin
                  c <= 1;
                  /*AUTORESET*/
              end
              else begin
                  a <= in_a;
                  b <= in_b;
                  c <= in_c;
              end
           end
        endmodule

Typing \[verilog-auto] will make this into:

...
                  c <= 1;
                  /*AUTORESET*/
                  // Beginning of autoreset for uninitialized flops
                  a <= 1'h0;
                  b <= 1'h0;
                  // End of automatics
        ...
(defalias 'verilog-auto-reset #[nil "\212\306 \307 \211\310	\311\")\312\n!\313\211\313\211%&\314\212\315\212\316\313\317'()\313**\204U�\320)('#\203U�\321\322\224!\203M�\320\323\313\317#\210\202-�\322\224\211*\2032�*,\210`)`\")!&\212\324\313\317'()\313**\204\226�\320)('#\203\226�\321\322\224!\203\216�\320\323\313\317#\210\202n�\322\224\211*\203s�*,\210\325 )\f\211+\322H)%\326\327\f\211+\322H)\f\211+\322H)\203\277�,\205\306�\f\211+\330H)\"\327\f\211+\331H)&\"\"\332
\333\"\211\205+\334c\210\335\336!\210
\203(\337
@\211-@)\"\206\367�
@-j\210-\211-@)\337-\211-@)%\"\203\340.P\202\341\342-!\343\261\210
A)\202\344�\335\344!.	\207" [indent-pt modi moddecls all-list sigss sig-list current-indentation verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-decls-get-signals nil verilog-signals-from-signame verilog-read-signals "\$@\\|\\<\\(begin\\|if\\|case[xz]?\\|always\\(_latch\\|_ff\\|_comb\$?\\)\\>\\)" t re-search-backward verilog-inside-comment-or-string-p 0 "[/\"]" "\$@\\|\\<\\(always\\(_latch\\|_ff\\|_comb\$?\\)\\>\\)" verilog-read-always-signals verilog-signals-not-in-struct append 1 2 sort verilog-signals-sort-compare "\n" verilog-insert-indent "// Beginning of autoreset for uninitialized flops\n" assoc " <= " " = " verilog-sig-tieoff ";\n" "// End of automatics" dly-list prereset-sigs noerror bound regexp pt sigs verilog-auto-reset-blocking-in-non sig verilog-assignment-delay] 7 (#$ . 386245) nil])
#@1721 Expand AUTOTIEOFF statements, as part of \[verilog-auto].
Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
signals to deasserted.

/*AUTOTIEOFF*/ is used to make stub modules; modules that have
the same input/output list as another module, but no internals.
Specifically, it finds all outputs in the module, and if that
input is not otherwise declared as a register or wire, nor comes
from a AUTOINST submodule's output, creates a tieoff. AUTOTIEOFF
does not examine assignments to determine what is already driven.

AUTORESET ties signals to deasserted, which is presumed to be zero.
Signals that match `verilog-active-low-regexp' will be deasserted by tying
them to a one.

You can add signals you do not want included in AUTOTIEOFF with
`verilog-auto-tieoff-ignore-regexp'.

`verilog-auto-wire-type' may be used to change the datatype of
the declarations.

`verilog-auto-reset-widths' may be used to change how the tieoff
value's width is generated.

An example of making a stub for another module:

module ExampMain
          #(parameter P)
          (input i, output o, inout io);
        endmodule

module ExampStub (/*AUTOARG*/);
            /*AUTOINOUTPARAM("ExampMain")*/
            /*AUTOINOUTMODULE("ExampMain")*/

/*AUTOTIEOFF*/

// verilator lint_off UNUSED
            wire _unused_ok = &{1\='b0,
                                /*AUTOUNUSED*/
                                1\='b0};
            // verilator lint_on  UNUSED
        endmodule

Typing \[verilog-auto] will make this into:

...
        /*AUTOTIEOFF*/
        // Beginning of automatic tieoffs
        wire [2:0] o = 3\='b0;
        // End of automatics
        ...
(defalias 'verilog-auto-tieoff #[nil "\212\306 \307 \211\310	\311\")	\310	\312\")\313\n\211\314H)\315\n\211\316H)\n\211\317H)\n\211\320H)\n\211\321H)\211\322H)\211\314H)\211\323H)&\"%\324%&\"\211%\205\277�\325 \210\326\327!\210\330\331%!\332\"%	%%\333	\311\316%$*\210%\203\274�%@'(\334\232\203\233�j\210\335'\211'@)\261\210\202\243�\336'(#\210\337\340\\]j\210\341\342'!\343\261\210%A%)\202y�\326\344!.\207" [indent-pt modi moddecls modsubdecls decls subdecls current-indentation verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-read-sub-decls verilog-signals-not-in 0 append 3 5 6 7 4 1 verilog-signals-not-matching-regexp verilog-forward-or-insert-line verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n" sort copy-alist verilog-signals-sort-compare verilog-modi-cache-add "assign" "assign " verilog-insert-one-definition 48 40 "= " verilog-sig-tieoff ";\n" "// End of automatics\n" sig-list verilog-auto-tieoff-ignore-regexp sig verilog-auto-tieoff-declaration] 12 (#$ . 389914) nil])
#@1127 Expand AUTOUNDEF statements, as part of \[verilog-auto].
Take any \=`defines since the last AUTOUNDEF in the current file
and create \=`undefs for them.  This is used to insure that
file-local defines do not pollute the global \=`define name space.

Limitations:
  AUTOUNDEF presumes any identifier following \=`define is the
  name of a define.  Any \=`ifdefs are ignored.

AUTOUNDEF suppresses creating an \=`undef for any define that was
  \=`undefed before the AUTOUNDEF.  This may be used to work around
  the ignoring of \=`ifdefs as shown below.

An example:

\=`define XX_FOO
        \=`define M_BAR(x)
        \=`define M_BAZ
        ...
        \=`ifdef NEVER
          \=`undef M_BAZ       // Emacs will see this and not \=`undef M_BAZ
        \=`endif
        ...
        /*AUTOUNDEF*/

Typing \[verilog-auto] will make this into:

...
        /*AUTOUNDEF*/
        // Beginning of automatic undefs
        \=`undef M_BAR
        \=`undef XX_FOO
        // End of automatics

You may also provide an optional regular expression, in which case only
defines the regular expression will be undefed.
(defalias 'verilog-auto-undef #[nil "\212\306\307\310\"\211@\311 `\312\211\212\313\314!\"\312##\204E�\315	\"!#\203E�\316\307\224!\203=�\315\317\312\314#\210\202�\307\224\211#\203#�#,\204N�eb\210\320\314!\"\312##\204\200�\321	\"!#\203\200�\316\307\224!\203x�\321\322\312\314#\210\202Y�\307\225\211#\203^�#,\203\310\312\224\205\243�\211\203\235�\323\224\225#\266\202\202\245�\324\224\225\"\266\202\325\232\203\342�\326\312\224\205\307�\211\203\301�\323\224\225#\266\202\202\311�\324\224\225\"\266\202	\203\325�\327	
\"\203N�
\f\235\204N�
\fB\202N�\330\326\312\224\205�\211\203\372�\323\224\225#\266\202\202\324\224\225\"\266\202\f\"\202N�)\331\f\332\"\211\205.\333 \210\334\335!\210\f\203+\334\336\f@\337#\210\fA\211\204\334\340!.\207" [params regexp indent-pt end-pt defs def verilog-read-auto-params 0 1 current-indentation nil "/\\*AUTOUNDEF\\>" t re-search-backward verilog-inside-comment-or-string-p "[/\"]" "`\$define\\|undef\$\\s-*\$[a-zA-Z_][a-zA-Z_0-9]*\$" re-search-forward "[/\"\n]" substring-no-properties buffer-substring-no-properties "define" 2 string-match delete sort string< verilog-forward-or-insert-line verilog-insert-indent "// Beginning of automatic undefs\n" "`undef " "\n" "// End of automatics\n" noerror bound pt] 8 (#$ . 392749)])
#@2213 Expand AUTOUNUSED statements, as part of \[verilog-auto].
Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
input and inout signals.

/*AUTOUNUSED*/ is used to make stub modules; modules that have the same
input/output list as another module, but no internals.  Specifically, it
finds all inputs and inouts in the module, and if that input is not otherwise
used, adds it to a comma separated list.

The comma separated list is intended to be used to create a _unused_ok
signal.  Using the exact name "_unused_ok" for name of the temporary
signal is recommended as it will insure maximum forward compatibility, it
also makes lint warnings easy to understand; ignore any unused warnings
with "unused" in the signal name.

To reduce simulation time, the _unused_ok signal should be forced to a
constant to prevent wiggling.  The easiest thing to do is use a
reduction-and with 1\='b0 as shown.

This way all unused signals are in one place, making it convenient to add
your tool's specific pragmas around the assignment to disable any unused
warnings.

You can add signals you do not want included in AUTOUNUSED with
`verilog-auto-unused-ignore-regexp'.

An example of making a stub for another module:

module ExampMain
          (input unused_input_a, input unused_input_b);
        endmodule

module ExampStub2 (/*AUTOARG*/);
            /*AUTOINOUTPARAM("ExampMain")*/
            /*AUTOINOUTMODULE("ExampMain")*/

/*AUTOTIEOFF*/

Typing \[verilog-auto] will make this into:

...
            // verilator lint_off UNUSED
            wire _unused_ok = &{1\='b0,
                                /*AUTOUNUSED*/
                                // Beginning of automatics
                                unused_input_a,
                                unused_input_b
                                // End of automatics
                                1\='b0};
            // verilator lint_on  UNUSED
        endmodule
(defalias 'verilog-auto-unused #[nil "\212\306\307!\210i\310 \211\311	\312\")	\311	\313\")\314\315\n\211\316H)\n\211\317H)\"\315\211\316H)\211\317H)\"\"\320\"\211\205z�\321 \210\322\323!\210\324\325!\326\"\203w�@j\210\211@)\327\261\210A)\202V�\322\330!.\207" [indent-pt modi moddecls modsubdecls decls subdecls search-backward "/*" verilog-modi-current verilog-modi-cache-results verilog-read-decls verilog-read-sub-decls verilog-signals-not-in append 2 1 verilog-signals-not-matching-regexp verilog-forward-or-insert-line verilog-insert-indent "// Beginning of automatic unused inputs\n" sort copy-alist verilog-signals-sort-compare ",\n" "// End of automatics\n" sig-list verilog-auto-unused-ignore-regexp sig] 7 (#$ . 395204) nil])
#@103 Convert an enum name SIGNM to an ascii string for insertion.
Remove user provided prefix ELIM-REGEXP.
(defalias 'verilog-enum-ascii #[(signm elim-regexp) "\204�\306\307\310\311\211\n
\312\313#\2037�\314

\f$\211G\312\224
G\\^\202�.\227)\207" [elim-regexp case-fold-search signm string literal fixedcase "_ DONT MATCH IT_" t "" nil 0 string-match replace-match to-string from-string start] 5 (#$ . 398199)])
#@2543 Expand AUTOASCIIENUM statements, as part of \[verilog-auto].
Create a register to contain the ASCII decode of an enumerated signal type.
This will allow trace viewers to show the ASCII name of states.

First, parameters are built into an enumeration using the synopsys enum
comment.  The comment must be between the keyword and the symbol.
(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)

Next, registers which that enum applies to are also tagged with the same
enum.

Finally, an AUTOASCIIENUM command is used.

The first parameter is the name of the signal to be decoded.

The second parameter is the name to store the ASCII code into.  For the
  signal foo, I suggest the name _foo__ascii, where the leading _ indicates
  a signal that is just for simulation, and the magic characters _ascii
  tell viewers like Dinotrace to display in ASCII format.

The third optional parameter is a string which will be removed
  from the state names.  It defaults to "" which removes nothing.

The fourth optional parameter is "onehot" to force one-hot
  decoding.  If unspecified, if and only if the first parameter
  width is 2^(number of states in enum) and does NOT match the
  width of the enum, the signal is assumed to be a one-hot
  decode.  Otherwise, it's a normal encoded state vector.

`verilog-auto-wire-type' may be used to change the datatype of
  the declarations.

"synopsys enum" may be used in place of "auto enum".

An example:

//== State enumeration
        parameter [2:0] // auto enum state_info
                           SM_IDLE =  3\='b000,
                           SM_SEND =  3\='b001,
                           SM_WAIT1 = 3\='b010;
        //== State variables
        reg [2:0]  /* auto enum state_info */
                   state_r;  /* auto state_vector state_r */
        reg [2:0]  /* auto enum state_info */
                   state_e1;

/*AUTOASCIIENUM("state_r", "state_ascii_r", "SM_")*/

Typing \[verilog-auto] will make this into:

...
        /*AUTOASCIIENUM("state_r", "state_ascii_r", "SM_")*/
        // Beginning of automatic ASCII enum decoding
        reg [39:0]              state_ascii_r;          // Decode of state_r
        always @(state_r) begin
           case ({state_r})
                SM_IDLE:  state_ascii_r = "idle ";
                SM_SEND:  state_ascii_r = "send ";
                SM_WAIT1: state_ascii_r = "wait1";
                default:  state_ascii_r = "%Erro";
           endcase
        end
        // End of automatics
(defalias 'verilog-auto-ascii-enum #[nil "\212\306\307\310\"\211@A@\3078\205�\3078\311\232?\205�\3078\3128\313 \314 \211<<\315<\316\")=\317=\211>\320H)=\211>\321H)\"?\322=!@\323	@\"\206^�\324\325\326 	#\211AB\310B8)\206q�\324\327\326 	#C\330\331?C\"\206\204�\324\332\326 C#\333\"D\334\335\f\206\217�\311\"\206\330�D@\211BA@)\203\303�D@B\336B\211BA@)!)AB\336B\211BA@)!)\232?\205\330�\337DG!AB\336B\211BA@)!)\232E\340\211FGD\211H\203FH@\211B@)G]FG\341H@\211B@)\"G]GHA\211H\204\350�)\342 \210\343\344!\210\n\345\346G\347_S\"\350	P\333\211\257CI\351<I\352
\333%\210)\343\353	\354#\210
J\\\343\355	\356#\210
K\\D\345\357E\203Y\360\202Z\361\347F]\\\nG$\362\363\340\320G^#LM\211H\203\271\343\345ME\205\364E\205\211\337DG!E\205\217\365H@\211B@)E\205\235\366\367\260\341H@\211B@)\"#\260!\210HA\211H\204u\343\345M\370L#!\210+
KZ\343\371!\210
JZ\343\372\373\".\207" [params undecode-name ascii-name elim-regexp one-hot-flag indent-pt verilog-read-auto-params 2 4 "" 3 current-indentation verilog-modi-current verilog-modi-cache-results verilog-read-decls append 6 7 verilog-decls-get-iovars assoc error "%s: Signal `%s' not found in design" verilog-point-text "%s: Signal `%s' does not have an enum tag" verilog-signals-not-in verilog-signals-matching-enum "%s: No state definitions for `%s'" nil string-match "onehot" verilog-make-width-expression number-to-string 0 verilog-enum-ascii verilog-forward-or-insert-line verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n" format "[%d:0]" 8 "Decode of " verilog-insert-definition "reg" "always @(" ") begin\n" "case ({" "})\n" "%%-%ds %s = \"%%-%ds\";\n" 9 1 substring "%Error" "(" "'b1<<" ")" ":" "default:" "endcase\n" "end\n" "// End of automatics\n" modi moddecls decls sig-list-consts sig-list-all undecode-sig sig undecode-enum enum-sigs one-hot enum-chars ascii-chars tmp-sigs decode-sig-list verilog-indent-level verilog-case-indent errname chrfmt] 10 (#$ . 398641)])
#@202 Replace Templated relative line numbers with absolute line numbers.
Internal use only.  This hacks around the line numbers in AUTOINST Templates
being different from the final output's line numbering.
(defalias 'verilog-auto-templated-rel #[nil "\303\211C\304eb\210m\204$�\305\306!\203�\nT	BT\304y\210\202\n�	\237eb\210\307\310\311\312#\205\203�\313\314\315\316\304\311\224\205S�\211\203M�\317\224\225#\266\202\202U�\320\224\225\"\266\202!	8\316\321\311\224\205v�\211\203p�\317\224\225#\266\202\202x�\320\224\225\"\266\202!\\!P\312\211#\210\202*�+\207" [buf-line template-line templateno 0 1 looking-at ".*AUTO_TEMPLATE" re-search-forward " Templated T\$[0-9]+\$ L\$[0-9]+\$" nil t replace-match " Templated " int-to-string string-to-number substring-no-properties buffer-substring-no-properties 2] 11 (#$ . 403236)])
#@89 Check AUTO_TEMPLATEs for unused lines.
Enable with `verilog-auto-template-warn-unused'.
(defalias 'verilog-auto-template-lint #[nil "\306 \206�\307 \212eb\210\310\311\312\313#\205[�\314 \211\315H\316\n@\nA@\"\312\203W�@A
\203%�\317\320\321\f8\322\f8\"
\"\204%�\323\324\f\322\234\325e`\"\\\f\326\234\f\315\234%\210\202%�,\202\f�*\207" [name1 tpl-info tpl-list tlines tpl-ass verilog-auto-template-hits buffer-file-name buffer-name re-search-forward "^\\s-*/?\\*?\\s-*[a-zA-Z0-9`_$]+\\s-+AUTO_TEMPLATE" nil t verilog-read-auto-template-middle 1 append gethash vector 2 3 verilog-warn-error "%s:%d: AUTO_TEMPLATE line unused: \".%s (%s)\"" count-lines 0] 8 (#$ . 404086)])
#@3515 Expand AUTO statements.
Look for any /*AUTO...*/ commands in the code, as used in
instantiations or argument headers.  Update the list of signals
following the /*AUTO...*/ command.

Use \[verilog-delete-auto] to remove the AUTOs.

Use \[verilog-diff-auto] to see differences in AUTO expansion.

Use \[verilog-inject-auto] to insert AUTOs for the first time.

Use \[verilog-faq] for a pointer to frequently asked questions.

For new users, we recommend setting `verilog-case-fold' to nil
and `verilog-auto-arg-sort' to t.

The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
called before and after this function, respectively.

For example:
        module ExampModule (/*AUTOARG*/);
            /*AUTOINPUT*/
            /*AUTOOUTPUT*/
            /*AUTOWIRE*/
            /*AUTOREG*/
            InstMod instName #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
        endmodule

You can also update the AUTOs from the shell using:
	emacs --batch  <filenames.v>  -f verilog-batch-auto
Or fix indentation with:
	emacs --batch  <filenames.v>  -f verilog-batch-indent
Likewise, you can delete or inject AUTOs with:
	emacs --batch  <filenames.v>  -f verilog-batch-delete-auto
	emacs --batch  <filenames.v>  -f verilog-batch-inject-auto
Or check if AUTOs have the same expansion
	emacs --batch  <filenames.v>  -f verilog-batch-diff-auto

Using \[describe-function], see also:
    `verilog-auto-arg'          for AUTOARG module instantiations
    `verilog-auto-ascii-enum'   for AUTOASCIIENUM enumeration decoding
    `verilog-auto-assign-modport' for AUTOASSIGNMODPORT assignment to/from modport
    `verilog-auto-inout'        for AUTOINOUT making hierarchy inouts
    `verilog-auto-inout-comp'   for AUTOINOUTCOMP copy complemented i/o
    `verilog-auto-inout-in'     for AUTOINOUTIN inputs for all i/o
    `verilog-auto-inout-modport'  for AUTOINOUTMODPORT i/o from an interface modport
    `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
    `verilog-auto-inout-param'  for AUTOINOUTPARAM copying params from elsewhere
    `verilog-auto-input'        for AUTOINPUT making hierarchy inputs
    `verilog-auto-insert-lisp'  for AUTOINSERTLISP insert code from lisp function
    `verilog-auto-insert-last'  for AUTOINSERTLAST insert code from lisp function
    `verilog-auto-inst'         for AUTOINST instantiation pins
    `verilog-auto-star'         for AUTOINST .* SystemVerilog pins
    `verilog-auto-inst-param'   for AUTOINSTPARAM instantiation params
    `verilog-auto-logic'        for AUTOLOGIC declaring logic signals
    `verilog-auto-output'       for AUTOOUTPUT making hierarchy outputs
    `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
    `verilog-auto-reg'          for AUTOREG registers
    `verilog-auto-reg-input'    for AUTOREGINPUT instantiation registers
    `verilog-auto-reset'        for AUTORESET flop resets
    `verilog-auto-sense'        for AUTOSENSE or AS always sensitivity lists
    `verilog-auto-tieoff'       for AUTOTIEOFF output tieoffs
    `verilog-auto-undef'        for AUTOUNDEF \=`undef of local \=`defines
    `verilog-auto-unused'       for AUTOUNUSED unused inputs/inouts
    `verilog-auto-wire'         for AUTOWIRE instantiation wires

`verilog-read-defines'      for reading \=`define values
    `verilog-read-includes'     for reading \=`includes

If you have bugs with these autos, please file an issue at
URL `https://www.veripool.org/verilog-mode' or contact the AUTOAUTHOR
Wilson Snyder (wsnyder@wsnyder.org).
(defalias 'verilog-auto #[(&optional inject) "\204�\306\307!\210\310\311!\203�\311 \210	\203\235\312 ?\205�\313 \n\314\211e\315@AB\316 \2043�\315CpD\212\315E\317 \210F\320=\204G�\320 \210\314G\321\322!\210)\323 \210\324 \210\325ed\"\210\326 \210p\315\211HI@J\203t�\327 \210\330\315\211\314#\210\331\332\333\"\210\334 pKL\335 \210M\203\221�\336 \210\337 \210\340 \210\331\341\342\"\210\331\343\344\"\210\331\345\346\"\210\331\347\350\"\210\331\351\352\"\210\331\353\354\"\210\331\355\356\"\210\331\357\360\"\210\331\361\362\"\210\331\363\364\"\210\331\365\366\"\210\331\367\370\"\210\331\371\372\"\210\331\373\374\"\210\331\375\376\"\210\331\377\201Y�\"\210\331\332\201Z�\"\210\331\201[�\201\\�\"\210\331\201]�\201^�\"\210\331\201_�\201`�\"\210\331\201a�\201b�\"\210\331\201c�\201d�\"\210\331\201e�\201f�\"\210\331\201g�\201h�\"\210\331\201i�\201j�\"\210\331\201k�\201l�\"\210N\203E\201m� \210O\203O\201n� \210-\314G\321\201o�!\210)P\203d\201p� \210\201q�\201Q�!\210\334 QB\203\220B\313 \232\203\220\201r�\315!\210?\205\232\306\201s�!\202\232?\205\232\306\201t�!.\207\314G\321\201u�!\210)deZ\201v�\201R�!\205\303R\205\303\201R�\201w�!\210\314S\201x�\201W�ed#\210\201y�\216\314\211TU\314V\315\211WX\312 ?\205\352\313 \n\314\211e\315@AB\316 \204�\315CpD\212\315E\317 \210F\320=\204\320 \210\314G\321\322!\210)\323 \210\324 \210\325ed\"\210\326 \210p\315\211HI@J\203A\327 \210\330\315\211\314#\210\331\332\333\"\210\334 pKL\335 \210M\203^\336 \210\337 \210\340 \210\331\341\342\"\210\331\343\344\"\210\331\345\346\"\210\331\347\350\"\210\331\351\352\"\210\331\353\354\"\210\331\355\356\"\210\331\357\360\"\210\331\361\362\"\210\331\363\364\"\210\331\365\366\"\210\331\367\370\"\210\331\371\372\"\210\331\373\374\"\210\331\375\376\"\210\331\377\201Y�\"\210\331\332\201Z�\"\210\331\201[�\201\\�\"\210\331\201]�\201^�\"\210\331\201_�\201`�\"\210\331\201a�\201b�\"\210\331\201c�\201d�\"\210\331\201e�\201f�\"\210\331\201g�\201h�\"\210\331\201i�\201j�\"\210\331\201k�\201l�\"\210N\203\201m� \210O\203\201n� \210-\314G\321\201o�!\210)P\2031\201p� \210\201q�\201Q�!\210\334 QB\203]B\313 \232\203]\201r�\315!\210?\205g\306\201s�!\202g?\205g\306\201t�!.\207" [noninteractive verilog-save-font-mod-hooked verilog-case-fold verilog-modi-cache-current verilog-modi-cache-current-max verilog-modi-cache-current-enable message "Updating AUTOs..." fboundp dinotrace-unannotate-all buffer-modified-p buffer-string t nil verilog-scan-cache-ok-p verilog-read-auto-template-init verilog-mode run-hooks verilog-before-auto-hook verilog-auto-reeval-locals verilog-read-auto-lisp-present verilog-read-auto-lisp verilog-getopt-flags verilog-read-includes verilog-read-defines verilog-auto-re-search-do "/\\*AUTOLOGIC\\*/" verilog-auto-logic-setup buffer-chars-modified-tick verilog-delete-auto-buffer verilog-inject-inst verilog-inject-sense verilog-inject-arg "/\\*AUTOINSERTLISP(.*?)\\*/" verilog-auto-insert-lisp "/\\*AUTOINSTPARAM\$(.*?)\$?\\*/" verilog-auto-inst-param "/\\*AUTOINST\$(.*?)\$?\\*/" verilog-auto-inst "\\.\\*" verilog-auto-star "/\\*AUTOASCIIENUM(.*?)\\*/" verilog-auto-ascii-enum "/\\*AUTOINOUTMODPORT(.*?)\\*/" verilog-auto-inout-modport "/\\*AUTOINOUTMODULE(.*?)\\*/" verilog-auto-inout-module "/\\*AUTOINOUTCOMP(.*?)\\*/" verilog-auto-inout-comp "/\\*AUTOINOUTIN(.*?)\\*/" verilog-auto-inout-in "/\\*AUTOINOUTPARAM(.*?)\\*/" verilog-auto-inout-param "/\\*AUTOOUTPUT\$(.*?)\$?\\*/" verilog-auto-output "/\\*AUTOINPUT\$(.*?)\$?\\*/" verilog-auto-input "/\\*AUTOINOUT\$(.*?)\$?\\*/" verilog-auto-inout "/\\*AUTOTIEOFF\\*/" verilog-auto-tieoff "/\\*AUTOUNDEF\$(.*?)\$?\\*/" verilog-auto-undef "/\\*AUTOASSIGNMODPORT(.*?)\\*/" verilog-dir-cache-preserving case-fold-search oldbuf verilog-scan-cache-tick verilog-scan-cache-preserving verilog-modi-cache-list major-mode verilog-in-hooks verilog-dir-cache-lib-filenames verilog-dir-cache-list verilog-auto-read-includes verilog-modi-cache-preserve-buffer verilog-modi-cache-preserve-tick inject verilog-auto-inst-template-numbers verilog-auto-template-warn-unused verilog-auto-delete-trailing-whitespace verilog-auto-update-tick font-lock-mode fontlocked inhibit-point-motion-hooks inhibit-modification-hooks verilog-no-change-functions before-change-functions after-change-functions verilog-auto-assign-modport verilog-auto-logic "/\\*AUTOWIRE\\*/" verilog-auto-wire "/\\*AUTOREG\\*/" verilog-auto-reg "/\\*AUTOREGINPUT\\*/" verilog-auto-reg-input "/\\*AUTOOUTPUTEVERY\$(.*?)\$?\\*/" verilog-auto-output-every "/\\*\$AUTOSENSE\\|AS\$\\*/" verilog-auto-sense "/\\*AUTORESET\\*/" verilog-auto-reset "/\\*AUTOUNUSED\\*/" verilog-auto-unused "/\\*AUTOARG\\*/" verilog-auto-arg "/\\*AUTOINSERTLAST(.*?)\\*/" verilog-auto-insert-last verilog-auto-templated-rel verilog-auto-template-lint verilog-auto-hook verilog-delete-trailing-whitespace make-local-variable verilog-restore-buffer-modified-p "Updating AUTOs...done (no changes)" "Updating AUTOs...done" verilog-before-save-font-hook boundp 0 run-hook-with-args #[nil "\303\304ed$\210	\203�\305\306!\210\306\307\310!)\207" [verilog-save-font-mod-hooked fontlocked verilog-in-hooks run-hook-with-args after-change-functions font-lock-mode t run-hooks verilog-after-save-font-hook] 5]] 7 (#$ . 404776) nil])
#@60 Keymap used in Verilog mode for smart template operations.
(defvar verilog-template-map (byte-code "\301 \302\303\304#\210\302\305\306#\210\302\307\310#\210\302\311\312#\210\302\313\314#\210\302\315\316#\210\302\317\320#\210\302\321\322#\210\302\323\324#\210\302\325\326#\210\302\327\330#\210\302\331\332#\210\302\333\334#\210\302\335\336#\210\302\337\340#\210\302\341\342#\210\302\343\344#\210\302\345\346#\210\302\347\350#\210\302\351\352#\210\302\353\354#\210\302\355\356#\210\302\357\360#\210\302\361\362#\210\302\363\364#\210\302\365\366#\210\302\367\370#\210\302\371\372#\210\302\373\374#\210\302\375\376#\210\302\377\201@�#\210)\207" [map make-sparse-keymap define-key "a" verilog-sk-always "b" verilog-sk-begin "c" verilog-sk-case "f" verilog-sk-for "g" verilog-sk-generate "h" verilog-sk-header "i" verilog-sk-initial "j" verilog-sk-fork "m" verilog-sk-module "o" verilog-sk-ovm-class "p" verilog-sk-primitive "r" verilog-sk-repeat "s" verilog-sk-specify "t" verilog-sk-task "u" verilog-sk-uvm-object "w" verilog-sk-while "x" verilog-sk-casex "z" verilog-sk-casez "?" verilog-sk-if ":" verilog-sk-else-if "/" verilog-sk-comment "A" verilog-sk-assign "F" verilog-sk-function "I" verilog-sk-input "O" verilog-sk-output "S" verilog-sk-state-machine "=" verilog-sk-inout "U" verilog-sk-uvm-component "W" verilog-sk-wire "R" verilog-sk-reg "D" verilog-sk-define-signal] 4) (#$ . 413604))
(byte-code "\302\303	#\210\304\305\306\307#\207" [verilog-mode-map verilog-template-map define-key "" put verilog-sk-prompt-condition no-self-insert t] 4)
#@535 Prompt for the loop condition.

This is a skeleton command (see `skeleton-insert').
Normally the skeleton text is inserted at point, with nothing "inside".
If there is a highlighted region, the skeleton text is wrapped
around the region text.

A prefix argument ARG says to wrap the skeleton around the next ARG words.
A prefix argument of -1 says to wrap around region, even if not highlighted.
A prefix argument of zero says to wrap around zero words---that is, nothing.
This is a way of overriding the use of a highlighted region.
(defalias 'verilog-sk-state-machine #[(&optional str arg) "\302\303	#\207" [str arg skeleton-proxy-new ("Name of state variable: " '(setq input "state") > "// State registers for " str | -23 n '(setq verilog-sk-state str) > "reg [" '(verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state 59 n '(setq input nil) > n > "// State FF for " verilog-sk-state n > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" n > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" n > verilog-sk-state " = next_" verilog-sk-state 59 n > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil) > n > "// Next State Logic for " verilog-sk-state n > "always @ ( /*AUTOSENSE*/ ) begin\n" > "case (" '(verilog-sk-prompt-state-selector) ") " n > ("case selector: " str ": begin" n > "next_" verilog-sk-state " = " _ ";" n > (- verilog-indent-level-behavioral) "end" n) resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil) > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))] 4 (#$ . 451189) "*P\nP"])
#@39 Regexp that matches the include file.
(defconst verilog-include-file-regexp "^`include\\s-+\"\$[^\n\"]*\$\"" (#$ . 452893))
#@51 Map containing mouse bindings for `verilog-mode'.
(defvar verilog-mode-mouse-map (byte-code "\302 \303	\"\210\304\305\306#\210\304\307\310#\210\304\311\312#\210)\207" [map verilog-mode-map make-sparse-keymap set-keymap-parent define-key "
" verilog-load-file-at-point [mouse-2] verilog-load-file-at-mouse [S-mouse-2] mouse-yank-at-click] 4) (#$ . 453025))
#@137 Colorize included files and modules in the (changed?) region.
Clicking on the middle-mouse button loads them in a buffer (as in dired).
(defalias 'verilog-highlight-region #[(beg end _old-len) "\204�	\205P\212\306 \307\216\310\211\311 \310\211&'\310(\312\216\313 \204(�\314)p*\314+,b\210\315 +-b\210\316 \210\317`+\"\211.\203r�\320.@\321\"\203i�\320.@\322\"\204c�\320.@\323\"\203i�\324.@!\210.A\211.\204H�)\203\274�\325/+\310#\203\274�\326\224b\210\327\326\224\326\225\"0\3300\331\310#\210\3300\332\310#\210\3300\333\310#\210\3300\322\310#\210\3300\334\335#\210\3300\3361#\210)\202w�-b\210	\205N\3371L\340+\310234\31455\204\375�\341432#\203\375�\342\343\224!\203\365�\341\344\314\310#\210\202\325�\343\225\2115\203\332�5,\205H\212\343\224b\210\342 \204D\345 \210\327\343\224\343\225\"0\3300\331\310#\210\3300\332\310#\210\3300\333\310#\210\3300\323\310#\210\3300\334\335#\210\3300\3361#\210))\202\310�0\202N\210\314.\f\207" [verilog-highlight-includes verilog-highlight-modules save-match-data-internal verilog-no-change-functions inhibit-point-motion-hooks #1=#:modified match-data #[nil "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3] t buffer-modified-p #[nil "?\205�\301\302!\207" [#1# restore-buffer-modified-p nil] 2] verilog-scan-cache-ok-p nil line-end-position beginning-of-line overlays-in overlay-get detachable verilog-include-file verilog-inst-module delete-overlay search-forward-regexp 1 make-overlay overlay-put start-closed end-closed evaporate mouse-face highlight local-map (error) "\$/\\*AUTOINST\\((.*?)\$?\\*/\\|\\.\\*\\)" re-search-forward verilog-inside-comment-or-string-p 0 "[/\"\n]" verilog-read-inst-module-matcher buffer-undo-list inhibit-read-only inhibit-modification-hooks verilog-scan-cache-tick verilog-scan-cache-preserving end-point end beg overlays verilog-include-file-regexp ov verilog-mode-mouse-map noerror bound regexp pt] 5 (#$ . 453394)])
#@62 Colorize included files and modules across the whole buffer.
(defalias 'verilog-highlight-buffer #[nil "\300ed\301#\207" [verilog-highlight-region nil] 4 (#$ . 455372) nil])
(defalias 'verilog-colorize-include-files-buffer 'verilog-highlight-buffer)
#@93 Load file under button 2 click's EVENT.
Files are checked based on `verilog-library-flags'.
(defalias 'verilog-load-file-at-mouse #[(event) "\212\301!\210\302\303!)\207" [event mouse-set-point verilog-load-file-at-point t] 2 (#$ . 455628) "@e"])
#@113 Load file under point.
If WARN, throw warning if not found.
Files are checked based on `verilog-library-flags'.
(defalias 'verilog-load-file-at-point #[(&optional warn) "\212\304``\"\305\211\203-�\204-�\306	@\307\"\203&�\310\311	@!\312	@!{!\210\313	A\211\204\f�\314 \210?\205\276�\315\n!\205\276�\316\317\305\224\205Y�\211\203S�\320\224\225#\266\202\202[�\321\224\225\"\266\202\322 \"@\203\264�\323\316\317\305\224\205\201�\211\203{�\320\224\225#\266\202\202\203�\321\224\225\"\266\202\322 \"@!\203\264�\324\316\317\305\224\205\252�\211\203\244�\320\224\225#\266\202\202\254�\321\224\225\"\266\202\322 \"@!\202\276�\205\276�\325\326\327\317!\"+\207" [hit overlays verilog-include-file-regexp warn overlays-in nil overlay-get verilog-inst-module verilog-goto-defun-file overlay-start overlay-end t beginning-of-line looking-at verilog-library-filenames 1 substring-no-properties buffer-substring-no-properties buffer-file-name file-readable-p find-file message "File `%s' isn't readable, use shift-mouse2 to paste in this field" match-string] 9 (#$ . 455882) nil])
#@68 Tell the user their current version, and where to get the FAQ etc.
(defalias 'verilog-faq #[nil "r\306\307!q\210p\310 \210	\311\211\312\211\312\313 \210\314\315!\210+\211\316\317\320\"!\210\316\321!\210\316\322!\210\316\321!\210\316\323!\210\316\321!\210\316\324!\210\316\321!\325!\210+\207" [default-directory #1=#:old-dir buffer-read-only buffer-file-name buffer-undo-list inhibit-modification-hooks get-buffer-create "*verilog-mode help*" kill-all-local-variables nil t erase-buffer run-hooks temp-buffer-setup-hook princ format "You are using verilog-mode %s\n" "\n" "For new releases, see https://www.veripool.org/verilog-mode\n" "For frequently asked questions, see https://www.veripool.org/verilog-mode-faq.html\n" "To submit a bug, use M-x verilog-submit-bug-report\n" internal-temp-output-buffer-show inhibit-read-only #2=#:buf standard-output verilog-mode-version] 5 (#$ . 456977) nil])
(autoload 'reporter-submit-bug-report "reporter")
#@50 Submit via mail a bug report on verilog-mode.el.
(defalias 'verilog-submit-bug-report #[nil "\303\304\305\306	P\307\310\211\311\n\312Q&)\207" [reporter-prompt-for-summary-p verilog-mode-version invocation-name t reporter-submit-bug-report "wsnyder@wsnyder.org" "verilog-mode v" (verilog-active-low-regexp verilog-after-save-font-hook verilog-align-ifelse verilog-assignment-delay verilog-auto-arg-sort verilog-auto-declare-nettype verilog-auto-delete-trailing-whitespace verilog-auto-endcomments verilog-auto-hook verilog-auto-ignore-concat verilog-auto-indent-on-newline verilog-auto-inout-ignore-regexp verilog-auto-input-ignore-regexp verilog-auto-inst-column verilog-auto-inst-dot-name verilog-auto-inst-interfaced-ports verilog-auto-inst-param-value verilog-auto-inst-sort verilog-auto-inst-template-numbers verilog-auto-inst-vector verilog-auto-lineup verilog-auto-newline verilog-auto-output-ignore-regexp verilog-auto-read-includes verilog-auto-reset-blocking-in-non verilog-auto-reset-widths verilog-auto-save-policy verilog-auto-sense-defines-constant verilog-auto-sense-include-inputs verilog-auto-star-expand verilog-auto-star-save verilog-auto-template-warn-unused verilog-auto-tieoff-declaration verilog-auto-tieoff-ignore-regexp verilog-auto-unused-ignore-regexp verilog-auto-wire-type verilog-before-auto-hook verilog-before-delete-auto-hook verilog-before-getopt-flags-hook verilog-before-save-font-hook verilog-cache-enabled verilog-case-fold verilog-case-indent verilog-cexp-indent verilog-compiler verilog-coverage verilog-delete-auto-hook verilog-getopt-flags-hook verilog-highlight-grouping-keywords verilog-highlight-includes verilog-highlight-modules verilog-highlight-translate-off verilog-indent-begin-after-if verilog-indent-declaration-macros verilog-indent-level verilog-indent-level-behavioral verilog-indent-level-declaration verilog-indent-level-directive verilog-indent-level-module verilog-indent-lists verilog-library-directories verilog-library-extensions verilog-library-files verilog-library-flags verilog-linter verilog-minimum-comment-distance verilog-mode-hook verilog-mode-release-emacs verilog-mode-version verilog-preprocessor verilog-simulator verilog-tab-always-indent verilog-tab-to-comment verilog-typedef-regexp verilog-warn-fatal) nil "Hi,\n\nI want to report a bug.\n\nBefore I go further, I want to say that Verilog mode has changed my life.\nI save so much time, my files are colored nicely, my co workers respect\nmy coding ability... until now.  I'd really appreciate anything you\ncould do to help me out with this minor deficiency in the product.\n\nI've taken a look at the Verilog-Mode FAQ at\nhttps://www.veripool.org/verilog-mode-faq.html.\n\nAnd, I've considered filing the bug on the issue tracker at\nhttps://www.veripool.org/verilog-mode-bugs\nsince I realize that public bugs are easier for you to track,\nand for others to search, but would prefer to email.\n\nSo, to reproduce the bug, start a fresh Emacs via " "\n-no-init-file -no-site-file'.  In a new buffer, in Verilog mode, type\nthe code included below.\n\nGiven those lines, I expected [[Fill in here]] to happen;\nbut instead, [[Fill in here]] happens!.\n\n== The code: =="] 9 (#$ . 457947) nil])
(provide 'verilog-mode)

${this.title}

Code Editor : verilog-mode.elc